[all-commits] [llvm/llvm-project] d28b4d: [RISCV] Lower BUILD_VECTOR with i64 type to VID on...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d28b4d89166fb705577a2d3a329006f0c0e0aacc
      https://github.com/llvm/llvm-project/commit/d28b4d89166fb705577a2d3a329006f0c0e0aacc
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-04-09 (Wed, 09 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Lower BUILD_VECTOR with i64 type to VID on RV32 if possible (#132339)

The element type i64 of the BUILD_VECTOR is not legal on RV32. It
doesn't catch the VID pattern after being legalized for i64.
So try to customized lower it to VID during type legalization.



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