[all-commits] [llvm/llvm-project] 5c2751: [RISCV] Support Load/Store Global assembler pseudo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c27511cb6ece1798e4503bcf8169359472871be
      https://github.com/llvm/llvm-project/commit/5c27511cb6ece1798e4503bcf8169359472871be
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-08 (Tue, 08 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    A llvm/test/MC/RISCV/rv32zilsd-pseudos.s

  Log Message:
  -----------
  [RISCV] Support Load/Store Global assembler pseudos for Zilsd. (#134950)

This adds support for 'ld \<rd\> \<symbol\>' and 'sd \<rd\>, \<symbol\>,
\<rt\>' to match what we do for RV32.

I've changed the interface to emitAuipcInstPair to use MCRegister
instead of MCOperand since we need to convert a GPRPair to GPR for
TmpReg for the load case.



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