[all-commits] [llvm/llvm-project] 9a762b: [RISCV] Reuse existing tablegen classes for Zilsd/...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e
      https://github.com/llvm/llvm-project/commit/9a762bb4e17969e69e4d1ce383fd0ccd41fb8e2e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-04-08 (Tue, 08 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td

  Log Message:
  -----------
  [RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)

We don't need pair specific classes. We just need to pass the pair
RegisterOperand to the existing classes we use for the base ISA and Zca.
For Zclsd, we need to changes the classes to take DAGOperand instead of
RegisterClass so we can pass a RegisterOperand.



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