[all-commits] [llvm/llvm-project] ad01e0: [RISCV][Xqcilo] Load/Store Pseudos (#134931)

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad01e0ac66441b28f9dc8acebd0dea5ea94a0f20
      https://github.com/llvm/llvm-project/commit/ad01e0ac66441b28f9dc8acebd0dea5ea94a0f20
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2025-04-08 (Tue, 08 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
    A llvm/test/MC/RISCV/xqcilo-pseudos-valid.s

  Log Message:
  -----------
  [RISCV][Xqcilo] Load/Store Pseudos (#134931)

This adds `qc.e.l<type> <reg>, <symbol>` and `qc.e.s<type> <reg>,
<symbol>, <reg>` pseudos for the corresponding Xqcilo instructions.

These emit as an AUIPC + (Standard) Load/Store pair, because this
sequence is shorter and can be relaxed back into the equivalent Xqcilo
load/store instruction in the right circumstances.



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