[all-commits] [llvm/llvm-project] ec0117: [LV] Compute register usage for interleaving on VP...

[Florian Hahn via All-commits]

  Branch: refs/heads/users/SamTebbs33/fhahn-vplan-reg-pressure-interleaving
  Home:   https://github.com/llvm/llvm-project
  Commit: ec0117ddf675a7838728ed18d613784dbf7b6c37
      https://github.com/llvm/llvm-project/commit/ec0117ddf675a7838728ed18d613784dbf7b6c37
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/i1-reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/LoongArch/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/X86/i1-reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
    M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll

  Log Message:
  -----------
  [LV] Compute register usage for interleaving on VPlan.

Add a version of calculateRegisterUsage that works estimates register
usage for a VPlan. This mostly just ports the existing code, with some
updates to figure out what recipes will generate vectors vs scalars.

There are number of changes in the computed register usages, but they
should be more accurate w.r.t. to the generated vector code.

There are the following changes:

 * Scalar usage increases in most cases by 1, as we always create a
   scalar canonical IV, which is alive across the loop and is not
   considered by the legacy implementation

 * Output is ordered by insertion, now scalar registers are added first
   due the canonical IV phi.

 * Using the VPlan, we now also more precisely know if an induction will
   be vectorized or scalarized.


  Commit: f2ad5d98a808937f708709fbe69fbffd98243f3b
      https://github.com/llvm/llvm-project/commit/f2ad5d98a808937f708709fbe69fbffd98243f3b
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll

  Log Message:
  -----------
  !fixup update after rebasing


  Commit: bc57c23bef4b5768ca2651528c83f7d3c11aad88
      https://github.com/llvm/llvm-project/commit/bc57c23bef4b5768ca2651528c83f7d3c11aad88
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

  Log Message:
  -----------
  !fixup address latest comments, thanks!


Compare: https://github.com/llvm/llvm-project/compare/ec0117ddf675%5E...bc57c23bef4b

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