[all-commits] [llvm/llvm-project] 9559f6: Revert "Revert "Reland "RegisterCoalescer: Add imp...

[Sander de Smalen via All-commits]

  Branch: refs/heads/users/sdesmalen-arm/srlt-reland-pr-123632
  Home:   https://github.com/llvm/llvm-project
  Commit: 9559f62a3ea0065af26adc1bc03e355d2287e08e
      https://github.com/llvm/llvm-project/commit/9559f62a3ea0065af26adc1bc03e355d2287e08e
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-04-02 (Wed, 02 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
    M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
    A llvm/test/CodeGen/AArch64/reduced-coalescer-issue.ll
    A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
    M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
    M llvm/test/CodeGen/PowerPC/frem.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/ldexp.ll
    M llvm/test/CodeGen/PowerPC/llvm.modf.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    A llvm/test/CodeGen/X86/pr76416.ll
    M llvm/test/CodeGen/X86/subreg-fail.mir
    A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
    M llvm/test/CodeGen/X86/vector-compress.ll

  Log Message:
  -----------
  Revert "Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)""

This reverts commit 6b1db79887df19bc8e8c946108966aa6021c8b87.


  Commit: c8cc773bffbd21a5686632ddfa2dd55b2758f27f
      https://github.com/llvm/llvm-project/commit/c8cc773bffbd21a5686632ddfa2dd55b2758f27f
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-04-04 (Fri, 04 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    M llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    M llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
    M llvm/test/CodeGen/X86/vector-compress.ll

  Log Message:
  -----------
  Only add implicit-def when tracking subreg liveness of the destination.

Otherwise, there's no point in adding the implicit-def.


  Commit: 875e23272295e53765d3bed0e7d3421d90dd7005
      https://github.com/llvm/llvm-project/commit/875e23272295e53765d3bed0e7d3421d90dd7005
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-04-04 (Fri, 04 Apr 2025)

  Changed paths:
    A llvm/test/CodeGen/X86/coalescer-subreg-to-reg-implicit-def-regression.mir

  Log Message:
  -----------
  Precommit test


  Commit: 16ac7acb24599e6ad5140eec517e87f475753287
      https://github.com/llvm/llvm-project/commit/16ac7acb24599e6ad5140eec517e87f475753287
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-04-04 (Fri, 04 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/X86/coalescer-subreg-to-reg-implicit-def-regression.mir

  Log Message:
  -----------
  Another fix (dead destination reg)


  Commit: b9d94065cb5ffa3a92f75f27db6bd3a8aec588b7
      https://github.com/llvm/llvm-project/commit/b9d94065cb5ffa3a92f75f27db6bd3a8aec588b7
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-04-04 (Fri, 04 Apr 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll

  Log Message:
  -----------
  Fix up tests after rebase


Compare: https://github.com/llvm/llvm-project/compare/9559f62a3ea0%5E...b9d94065cb5f

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications