[all-commits] [llvm/llvm-project] bf388f: [AMDGPU][True16][CodeGen] legalize operands when m...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf388f8a43c26264dfa96a91bead440d19f58bc4
      https://github.com/llvm/llvm-project/commit/bf388f8a43c26264dfa96a91bead440d19f58bc4
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir

  Log Message:
  -----------
  [AMDGPU][True16][CodeGen] legalize operands when move16bit SALU to VALU (#133985)

This is a follow up PR from
https://github.com/llvm/llvm-project/pull/132089.

When a V2S copy and its useMI are lowered to VALU,  this patch check:
If the generated new VALU is a true16 inst. Add subreg access on all
operands if necessary.

an example MIR looks like:
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:sreg_32 = COPY %1:vgpr_32
%3:sreg_32 = S_FLOOR_F16 %2:sreg_32, ...
```
currently lowered to
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:vgpr_16 = V_FLOOR_F16_t16_e64 0, %1:vgpr_32, 0, 0, 0 ...
```
after this patch
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:vgpr_16 = V_FLOOR_F16_t16_e64 0, %1.lo16:vgpr_32, 0, 0, 0 ...
```



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications