[all-commits] [llvm/llvm-project] ae8ad8: [Clang][AArch64] Model ZT0 table using inaccessibl...

[Lukacma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ae8ad8649da7f69dae2b19db79b69c460be01916
      https://github.com/llvm/llvm-project/commit/ae8ad8649da7f69dae2b19db79b69c460be01916
  Author: Lukacma <Marian.Lukac at arm.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td

  Log Message:
  -----------
  [Clang][AArch64] Model ZT0 table using inaccessible memory (#133727)

This patch changes how ZT0 table is modelled at LLVM-IR level. Currently
accesses to ZT0 are represented at LLVM-IR level as memory reads and
writes. This patch changes that and models them as purely Inaccessible
memory accesses without any unmodeled side-effects.



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