[all-commits] [llvm/llvm-project] 41a6bb: [LLVM][CodeGen][SVE] Prefer NEON instructions when...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41a6bb4c055cf08110676d9bc942f369fb19450d
      https://github.com/llvm/llvm-project/commit/41a6bb4c055cf08110676d9bc942f369fb19450d
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-04-03 (Thu, 03 Apr 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
    M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
    M llvm/test/CodeGen/AArch64/load-insert-zero.ll
    M llvm/test/CodeGen/AArch64/sinksplat.ll
    M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
    M llvm/test/CodeGen/AArch64/sve-fcmp.ll
    M llvm/test/CodeGen/AArch64/sve-fcvt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fp-combine.ll
    M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
    M llvm/test/CodeGen/AArch64/sve-int-log.ll
    M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll
    M llvm/test/CodeGen/AArch64/sve-knownbits.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-pr92779.ll
    M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
    M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
    M llvm/test/CodeGen/AArch64/sve-zeroinit.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfadd.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmax.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmaxnm.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmin.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfminnm.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfsub.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-counts-not.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-ext.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvt-bfcvt.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvtlt-fcvtx.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvtzsu.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-flogb.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-frint-frecpx-fsqrt.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-rev.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-urecpe-ursqrte-sqabs-sqneg.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-uscvtf.ll

  Log Message:
  -----------
  [LLVM][CodeGen][SVE] Prefer NEON instructions when zeroing Z registers. (#133929)

Several implementations have zero-latency instructions to zero
registers. To-date no implementation has a dedicated SVE instruction but
we can use the NEON equivalent because it is defined to zero bits
128..VL regardless of the immediate used.

NOTE: The relevant instruction is not available in streaming mode, where
the original SVE DUP instruction remains in use.



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