[all-commits] [llvm/llvm-project] 536fe7: [RISCV] Modify register type of extd* Xqcibm instr...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 536fe74aaac437e147fc64dada6af8aab79a8b54
      https://github.com/llvm/llvm-project/commit/536fe74aaac437e147fc64dada6af8aab79a8b54
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-04-02 (Wed, 02 Apr 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
    M llvm/test/MC/RISCV/xqcibm-invalid.s
    M llvm/test/MC/RISCV/xqcibm-valid.s

  Log Message:
  -----------
  [RISCV] Modify register type of extd* Xqcibm instructions (#134027)

The v0.8 spec specifies that rs1 cannot be x31 (t6) since these
instructions operate on a pair of registers (rs1 and rs1 + 1) with no wrap
around.

The latest spec can be found here:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.8.0



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