[all-commits] [llvm/llvm-project] 337bad: [EarlyIfConverter] Fix reg killed twice after earl...

[Afanasyev Ivan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 337bad3921356fba89409e03793f7d2df846c0e9
      https://github.com/llvm/llvm-project/commit/337bad3921356fba89409e03793f7d2df846c0e9
  Author: Afanasyev Ivan <ivafanas at gmail.com>
  Date:   2025-04-01 (Tue, 01 Apr 2025)

  Changed paths:
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    A llvm/test/CodeGen/AArch64/early-ifcvt-on-double-killed-reg.mir
    A llvm/test/CodeGen/Hexagon/early-if-predicator-reg-killed-everywhere.mir

  Log Message:
  -----------
  [EarlyIfConverter] Fix reg killed twice after early-if-predicator and ifcvt (#133554)

Bug relates to `early-if-predicator` and `early-ifcvt` passes. If
virtual register has "killed" flag in both basic blocks to be merged
into head, both instructions in head basic block will have "killed" flag
for this register. It makes MIR incorrect.

Example:

```
  bb.0: ; if
    ...
    %0:intregs = COPY $r0
    J2_jumpf %2, %bb.2, implicit-def dead $pc
    J2_jump %bb.1, implicit-def dead $pc

  bb.1: ; if.then
    ...
    S4_storeiri_io killed %0, 0, 1
    J2_jump %bb.3, implicit-def dead $pc

  bb.2: ; if.else
    ...
    S4_storeiri_io killed %0, 0, 1
    J2_jump %bb.3, implicit-def dead $pc
```

After early-if-predicator will become:

```
  bb.0:
    %0:intregs = COPY $r0
    S4_storeirif_io %1, killed %0, 0, 1
    S4_storeirit_io %1, killed %0, 0, 1
```

Having `killed` flag set twice in bb.0 for `%0` is an incorrect MIR.



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