[all-commits] [llvm/llvm-project] d6d1db: [ARM] Speedups for CombineBaseUpdate. (#129725)

[David Green via All-commits]

  Branch: refs/heads/release/20.x
  Home:   https://github.com/llvm/llvm-project
  Commit: d6d1dbf221814b2a28cb234e72c7d81730ff26e7
      https://github.com/llvm/llvm-project/commit/d6d1dbf221814b2a28cb234e72c7d81730ff26e7
  Author: David Green <david.green at arm.com>
  Date:   2025-03-31 (Mon, 31 Mar 2025)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp

  Log Message:
  -----------
  [ARM] Speedups for CombineBaseUpdate. (#129725)

This attempts to put limits onto CombineBaseUpdate for degenerate cases
like #127477. The biggest change is to add a limit to the number of base
updates to check in CombineBaseUpdate. 64 is hopefully plenty high
enough for most runtime unrolled loops to generate postinc where they
are beneficial.

It also moves the check for isValidBaseUpdate later so that it only
happens if we will generate a valid instruction. The 1024 limit to
hasPredecessorHelper comes from the X86 backend, which uses the same
limit.

I haven't added a test case as it would need to be very big and my
attempts at generating a smaller version did not show anything useful.

Fixes #127477.

(cherry picked from commit 86cf4ed7e9510a6828e95e8b36893eec116c9cf9)



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