[all-commits] [llvm/llvm-project] ea06f7: [RISCV] For RV32C, disassembly of c.slli should fa...

[Paul Bowen-Huggett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea06f7f96fb1ce5a77439cf1a26f97c2f2488648
      https://github.com/llvm/llvm-project/commit/ea06f7f96fb1ce5a77439cf1a26f97c2f2488648
  Author: Paul Bowen-Huggett <paulhuggett at mac.com>
  Date:   2025-03-31 (Mon, 31 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    A llvm/test/MC/Disassembler/RISCV/c_slli.txt

  Log Message:
  -----------
  [RISCV] For RV32C, disassembly of c.slli should fail when immediate > 31 (#133713)

Fixes #133712.

The change causes `c.slli` instructions whose immediate has bit 5 set to
be rejected when disassembling RV32C. Added a test to exhaustively cover
c.slli for 32 bit targets. A minor tweak to make the debug output a
little more readable.

The spec. (20240411) says:

> For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are
designated for custom extensions. For RV32C and RV64C, the shift amount
must be non-zero; the code points with shamt=0 are HINTs. For all base
ISAs, the code points with rd=x0 are HINTs, except those with shamt[5]=1
in RV32C.



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