[all-commits] [llvm/llvm-project] 4e4cb4: [RISCV][MC] Enable printing of zext.b alias (#133502)

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e4cb4359ae915b5a14c94914e39a8cc94e98963
      https://github.com/llvm/llvm-project/commit/4e4cb4359ae915b5a14c94914e39a8cc94e98963
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2025-03-28 (Fri, 28 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/abdu-neg.ll
    M llvm/test/CodeGen/RISCV/abdu.ll
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/avgceilu.ll
    M llvm/test/CodeGen/RISCV/avgflooru.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
    M llvm/test/CodeGen/RISCV/csr-first-use-cost.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/fold-mem-offset.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr65025.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/CodeGen/RISCV/simplify-condbr.ll
    M llvm/test/CodeGen/RISCV/split-store.ll
    M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
    M llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll
    M llvm/test/MC/RISCV/rv32i-aliases-valid.s
    M llvm/test/MC/RISCV/rv64i-aliases-valid.s

  Log Message:
  -----------
  [RISCV][MC] Enable printing of zext.b alias (#133502)

The comment shows that at the time we were worried about producing the
alias in assembly that might be ingested by a binutils version that
doesn't yet support it. binutils gained support over 4 years ago
<https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e>.
With all the changes in areas such as ELF attributes, if you tried to
use LLVM's RISC-V assembler output with a binutils that old then zext.b
would be the least of your worries.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications