[all-commits] [llvm/llvm-project] a48145: [RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyIn...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a481452cd88acc180f82dd5631257c8954ed7812
      https://github.com/llvm/llvm-project/commit/a481452cd88acc180f82dd5631257c8954ed7812
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2025-03-28 (Fri, 28 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyInstrImpl (#132002)

This adds coverage for additional instructions in isCopyInstrImpl, for
now picking just those where I can observe that there is a codegen
difference for SPEC.

This allows MachineCopyPropagation to successfully eliminate no-op moves in this form.



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