[all-commits] [llvm/llvm-project] 96e5ee: [BOLT][AArch64] Add partial support for lite mode ...

[Maksim Panchenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 96e5ee23a76136851a52f48c780249e2a86a5ce9
      https://github.com/llvm/llvm-project/commit/96e5ee23a76136851a52f48c780249e2a86a5ce9
  Author: Maksim Panchenko <maks at fb.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M bolt/include/bolt/Core/BinaryContext.h
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/include/bolt/Core/MCPlusBuilder.h
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Passes/BinaryPasses.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
    A bolt/test/AArch64/lite-mode.s

  Log Message:
  -----------
  [BOLT][AArch64] Add partial support for lite mode (#133014)

In lite mode, we only emit code for a subset of functions while
preserving the original code in .bolt.org.text. This requires updating
code references in non-emitted functions to ensure that:

* Non-optimized versions of the optimized code never execute.
* Function pointer comparison semantics is preserved.

On x86-64, we can update code references in-place using "pending
relocations" added in scanExternalRefs(). However, on AArch64, this is
not always possible due to address range limitations and linker address
"relaxation".

There are two types of code-to-code references: control transfer (e.g.,
calls and branches) and function pointer materialization.
AArch64-specific control transfer instructions are covered by #116964.

For function pointer materialization, simply changing the immediate
field of an instruction is not always sufficient. In some cases, we need
to modify a pair of instructions, such as undoing linker relaxation and
converting NOP+ADR into ADRP+ADD sequence.

To achieve this, we use the instruction patch mechanism instead of
pending relocations. Instruction patches are emitted via the regular MC
layer, just like regular functions. However, they have a fixed address
and do not have an associated symbol table entry. This allows us to make
more complex changes to the code, ensuring that function pointers are
correctly updated. Such mechanism should also be portable to RISC-V and
other architectures.

To summarize, for AArch64, we extend the scanExternalRefs() process to
undo linker relaxation and use instruction patches to partially
overwrite unoptimized code.



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