[all-commits] [llvm/llvm-project] d131b7: [RISCV] Disable i1 fixed vectors with more than 10...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d131b78e060c709d41ba55572a5639f8e9f7ecc0
      https://github.com/llvm/llvm-project/commit/d131b78e060c709d41ba55572a5639f8e9f7ecc0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/pr133217.ll

  Log Message:
  -----------
  [RISCV] Disable i1 fixed vectors with more than 1024 elements. (#133267)

v2048i1 is an MVT, but v2048i8 is not so we don't support i8 vectors
with more than 1024 elements. Lowering a v2048i1 shufflevector would
requires promoting to v2048i8. Since v2048i8 isn't legal and isn't an
MVT this leads to a crash.

To fix the crash, this patch makes v2048i1 an illegal type.



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