[all-commits] [llvm/llvm-project] ebe1ec: [TableGen][RISCV] Support sub-operands in Compress...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ebe1ece4bbfdcd29dd2b578f466998970f28a333
      https://github.com/llvm/llvm-project/commit/ebe1ece4bbfdcd29dd2b578f466998970f28a333
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    A llvm/test/TableGen/CompressInstEmitter/suboperands.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen][RISCV] Support sub-operands in CompressInstEmitter.cpp. (#133039)

I'm looking into using sub-operands for memory operands. This would use
MIOperandInfo to create a single operand that contains a register and
immediate as sub-operands. We can treat this as a single operand for
parsing and matching in the assembler. I believe this will provide some
simplifications like removing the InstAliases we need to support "(rs1)"
without an immediate.

Doing this requires making CompressInstEmitter aware of sub-operands.

I've chosen to use a flat list of operands in the CompressPats so each
sub-operand is represented individually.



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