[all-commits] [llvm/llvm-project] aa207c: [RISCV] Update the latency of floating point load ...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa207c3f054abb630be61cd60a11840a5c341c19
      https://github.com/llvm/llvm-project/commit/aa207c3f054abb630be61cd60a11840a5c341c19
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s

  Log Message:
  -----------
  [RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165)

P500-series cores should have a floating point load latency closer to 5
cycles, just like P400- and P600-series cores.



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