[all-commits] [llvm/llvm-project] 0ae618: [RISCV] Manually update MIR inputs to reflect #79e...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ae6185b455876b98cf58888117e3043cb43d060
      https://github.com/llvm/llvm-project/commit/0ae6185b455876b98cf58888117e3043cb43d060
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Manually update MIR inputs to reflect #79e82b6

Since we've changed what get's generated, we should update the snapshots
of MIR.  Otherwise, we end up testing configurations which are no longer
possible from codegen.



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