[all-commits] [llvm/llvm-project] 0572a3: AMDGPU/GlobalISel: add RegBankLegalize rules for b...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/shifts
  Home:   https://github.com/llvm/llvm-project
  Commit: 0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f
      https://github.com/llvm/llvm-project/commit/0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg

Uniform S16 shifts have to be extended to S32 using appropriate Extend
before lowering to S32 instruction.
Uniform packed V2S16 are lowered to SGPR S32 instructions,
other option is to use VALU packed V2S16 and ReadAnyLane.
For uniform S32 and S64 and divergent S16, S32, S64 and V2S16 there are
instructions available.



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