[all-commits] [llvm/llvm-project] b9666c: [RISCV] Reverse the order of Base and Offset in Co...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9666cf2034e103ef28280fae61f43fae7e28192
      https://github.com/llvm/llvm-project/commit/b9666cf2034e103ef28280fae61f43fae7e28192
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

  Log Message:
  -----------
  [RISCV] Reverse the order of Base and Offset in Core-V RegReg operand. (#133209)

This puts the base before the offset to match the order we use for base
ISA where the offset is an immediate.

I'm investigating using sub-operands for the base ISA loads and stores
too so having a consistent operand order will allow more sharing.



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