[all-commits] [llvm/llvm-project] a6e561: [RISCV] Modify operand regclass in load store patt...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6e56162c251db180f4618202c8088acba311ce8
      https://github.com/llvm/llvm-project/commit/a6e56162c251db180f4618202c8088acba311ce8
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-03-27 (Thu, 27 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] Modify operand regclass in load store patterns (#133071)

$rs1 is defined as GPRMem in the correspoding instruction definition
classes.



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