[all-commits] [llvm/llvm-project] d58f57: [RISCV] Use named sub-operands to simplify encodin...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d58f57228d46a73059d507eef252a8dfae14f256
      https://github.com/llvm/llvm-project/commit/d58f57228d46a73059d507eef252a8dfae14f256
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-26 (Wed, 26 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

  Log Message:
  -----------
  [RISCV] Use named sub-operands to simplify encoding/decoding for CoreV Reg-Reg instructions. (#133181)

We can name the sub-operands using a DAG in the 'ins'. This allows those
names to be matched to the encoding fields. This removes the need for a
custom encoder/decoder that treats the 2 sub-operands as a single 10-bit
value.

While doing this, I noticed the base and offset names in the
MIOperandInfo were swapped relative to how the operands are parsed and
printed. Assuming that I've correctly understood the parsing/print
format as "offset(base)".



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