[all-commits] [llvm/llvm-project] 79e82b: [RISCV] Use a precise size for MMO on scalable spi...

Philip Reames via All-commits all-commits at lists.llvm.org
Wed Mar 26 18:26:20 PDT 2025 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79e82b6f146e39b2498b9eb44033cde8659ba6b7
      https://github.com/llvm/llvm-project/commit/79e82b6f146e39b2498b9eb44033cde8659ba6b7
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-03-26 (Wed, 26 Mar 2025)

  Changed paths:
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/pr69586.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/expandload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/remat.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.ll
    M llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir
    M llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Use a precise size for MMO on scalable spill and fill (#133171)

The primary effect of this is that we get proper scalable sizes printed
by the assembler, but this may also enable proper aliasing analysis. I
don't see any test changes resulting from the later.

Getting the size is slightly tricky as we store the scalable size as a
non-scalable quantity in the object size field for the frame index. We
really should remove that hack at some point...

For the synthetic tuple spills and fills, I dropped the size from the
split loads and stores to avoid incorrect (overly large) sizes. We could
also divide by the NF factor if we felt like writing the code to do so.



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