[all-commits] [llvm/llvm-project] 7b146a: [LV] Compute register usage for interleaving on VP...
Sam Tebbs via All-commits
all-commits at lists.llvm.org
Wed Mar 26 06:59:09 PDT 2025
Branch: refs/heads/users/SamTebbs33/reg-pressure
Home: https://github.com/llvm/llvm-project
Commit: 7b146a6e16b812ae954b3edb58ee8a3e4c65c9be
https://github.com/llvm/llvm-project/commit/7b146a6e16b812ae954b3edb58ee8a3e4c65c9be
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/i1-reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/i1-reg-usage.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll
Log Message:
-----------
[LV] Compute register usage for interleaving on VPlan.
Add a version of calculateRegisterUsage that works estimates register
usage for a VPlan. This mostly just ports the existing code, with some
updates to figure out what recipes will generate vectors vs scalars.
There are number of changes in the computed register usages, but they
should be more accurate w.r.t. to the generated vector code.
There are the following changes:
* Scalar usage increases in most cases by 1, as we always create a
scalar canonical IV, which is alive across the loop and is not
considered by the legacy implementation
* Output is ordered by insertion, now scalar registers are added first
due the canonical IV phi.
* Using the VPlan, we now also more precisely know if an induction will
be vectorized or scalarized.
Commit: bcb34cdc2887e94a8465a95c6c0eb84452837dcc
https://github.com/llvm/llvm-project/commit/bcb34cdc2887e94a8465a95c6c0eb84452837dcc
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
Log Message:
-----------
!fixup update after rebasing
Commit: 07b2a1e12e6ef4c8fc3039a02ba195f3a6e166d2
https://github.com/llvm/llvm-project/commit/07b2a1e12e6ef4c8fc3039a02ba195f3a6e166d2
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
!fixup address latest comments, thanks!
Commit: 43c98be25e6e59958eb53d7216273e9aa3012e98
https://github.com/llvm/llvm-project/commit/43c98be25e6e59958eb53d7216273e9aa3012e98
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reduces-vf.ll
M llvm/test/Transforms/LoopVectorize/X86/reg-usage.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
Log Message:
-----------
[LoopVectorizer] Prune VFs based on plan register pressure
Based on fhahn's work at https://github.com/llvm/llvm-project/pull/126437 .
This PR moves the register usage checking to after the plans are
created, so that any recipes that optimise register usage (such as
partial reductions) can be properly costed and not have their VF pruned
unnecessarily.
It involves changing some tests, notably removing one from
mve-known-tripcount.ll due to it not being vectorisable thanks to high
register pressure. tail-folding-reduces-vf.ll was modified to reduce its
register pressure but still test what was intended.
Commit: bdcb51d42e5868b98e45d969b51799b596b64d60
https://github.com/llvm/llvm-project/commit/bdcb51d42e5868b98e45d969b51799b596b64d60
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
Format
Commit: ad3ee1c3007dd55279464f80f6c4b82fc5830093
https://github.com/llvm/llvm-project/commit/ad3ee1c3007dd55279464f80f6c4b82fc5830093
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
Log Message:
-----------
Ignore in-loop reductions
Commit: 823219a6b7f0cf3c3d093961929c7bf3c8f9e033
https://github.com/llvm/llvm-project/commit/823219a6b7f0cf3c3d093961929c7bf3c8f9e033
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
Simpify in-loop checking
Commit: 07e3adfd61fdb3759c17d368b46374ff4752d8b2
https://github.com/llvm/llvm-project/commit/07e3adfd61fdb3759c17d368b46374ff4752d8b2
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-25 (Tue, 25 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
Log Message:
-----------
Re-add tripcount test
Commit: 0a0cfea135d465374fe20eeb049a4ed6065ec4ff
https://github.com/llvm/llvm-project/commit/0a0cfea135d465374fe20eeb049a4ed6065ec4ff
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-26 (Wed, 26 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
Log Message:
-----------
Revert scalable-call.ll changes
Commit: 67d09bdc6bd30b3673620ee1e8cfec07809b21d1
https://github.com/llvm/llvm-project/commit/67d09bdc6bd30b3673620ee1e8cfec07809b21d1
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-26 (Wed, 26 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
Set MaxVF without loop if MaxVectorElementCount <= MaxVectorElementCountMaxBW
Commit: 410afea0e04f80e885c757d8fa5b589a4852f361
https://github.com/llvm/llvm-project/commit/410afea0e04f80e885c757d8fa5b589a4852f361
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-26 (Wed, 26 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
Move calculateRegisterUsage out of cost model
Commit: 5f81501485b6c9d3e6a35fd382e1c10634e9658c
https://github.com/llvm/llvm-project/commit/5f81501485b6c9d3e6a35fd382e1c10634e9658c
Author: Samuel Tebbs <samuel.tebbs at arm.com>
Date: 2025-03-26 (Wed, 26 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
Separate out scaled reduction changes
Compare: https://github.com/llvm/llvm-project/compare/7b146a6e16b8%5E...5f81501485b6
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