[all-commits] [llvm/llvm-project] f4bb9b: [MCA] Extend -instruction-tables option with verbo...

[Julien Villette via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f4bb9b53ad09739ae120df66a317c9b89ddcaff0
      https://github.com/llvm/llvm-project/commit/f4bb9b53ad09739ae120df66a317c9b89ddcaff0
  Author: Julien Villette <julien.villette at gmail.com>
  Date:   2025-03-25 (Tue, 25 Mar 2025)

  Changed paths:
    M llvm/docs/CommandGuide/llvm-mca.rst
    M llvm/include/llvm/MC/MCSchedule.h
    M llvm/lib/MC/MCSchedule.cpp
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
    M llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
    M llvm/tools/llvm-mca/Views/InstructionInfoView.h
    M llvm/tools/llvm-mca/llvm-mca.cpp

  Log Message:
  -----------
  [MCA] Extend -instruction-tables option with verbosity levels (#130574)

Option becomes: -instruction-tables=`<level>`
 
The choice of `<level>` controls number of printed information.
`<level>` may be `none` (default), `normal`, `full`.
Note: If the option is used without `<label>`, default is `normal`
(legacy).

When `<level>` is `full`, additional information are:
- `<Bypass Latency>`: Latency when a bypass is implemented between
operands
  in pipelines (see SchedReadAdvance).
  - `<LLVM Opcode Name>`: mnemonic plus operands identifier.
  - `<Resources units>`: Used resources associated with LLVM Opcode.
- `<instruction comment>`: reports comment if any from source assembly.

Level `full` can be used to better check scheduling info when TableGen
is modified.
LLVM Opcode name help to find right instruction regexp to fix TableGen
Scheduling Info.

-instruction-tables=full option is validated on
AArch64/Neoverse/V1-sve-instructions.s

Follow up of MR #126703

---------

Co-authored-by: Julien Villette <julien.villette at sipearl.com>



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