[all-commits] [llvm/llvm-project] 776484: [MC] Account for AcquireAtCycle in getReciprocalTh...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 77648476f28c4ee50eb2ffca952453a210386d7d
      https://github.com/llvm/llvm-project/commit/77648476f28c4ee50eb2ffca952453a210386d7d
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-03-24 (Mon, 24 Mar 2025)

  Changed paths:
    M llvm/lib/MC/MCSchedule.cpp
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/disable-im.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/no-vsetvli-to-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/reductions.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/strided-load-store.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/strided-load-x0.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vector-integer-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vle-vse.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-sew-instrument.s

  Log Message:
  -----------
  [MC] Account for AcquireAtCycle in getReciprocalThroughput (#132653)

Previously `MCSchedModel::getReciprocalThroughput` ignored
`AcquireAtCycle` completey, this patch fixes it by using the largest
`(ReleaseAtCycle - AcquireAtCycle) / NumUnits` as inverse throughput.

Here are some technical explanations:
https://myhsu.xyz/llvm-sched-interval-throughput

---------

Co-authored-by: Julien Villette <julien.villette at sipearl.com>



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