[all-commits] [llvm/llvm-project] 02ed65: [AMDGPU] 4-align TTMP triples (#132759)

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02ed65912ea36ddbb280c959eebb5df129fa3dfa
      https://github.com/llvm/llvm-project/commit/02ed65912ea36ddbb280c959eebb5df129fa3dfa
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2025-03-24 (Mon, 24 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll

  Log Message:
  -----------
  [AMDGPU] 4-align TTMP triples (#132759)

Follow up to e4284a7c70cd "[AMDGPU] 4-align SGPR triples".

Previously TTMP triples like ttmp[3:5] were aligned on a 3-TTMP boundary
which has no basis in hardware.

Aligning them on a 4-TTMP boundary matches what we do for SGPRs, which
reduces the number of extra register classes synthesized by TableGen,
bringing the total number down from 653 to 615.



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