[all-commits] [llvm/llvm-project] 9d92d4: [RISCV] Add alias names for tdata1 and tdata3 CSRs...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d92d4b01ce0ddfdcbb2bd5ec0ec3208ad480ccc
      https://github.com/llvm/llvm-project/commit/9d92d4b01ce0ddfdcbb2bd5ec0ec3208ad480ccc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-23 (Sun, 23 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/machine-csr-names.s

  Log Message:
  -----------
  [RISCV] Add alias names for tdata1 and tdata3 CSRs. (#132525)

The RISC-V Debug Specification defines multiple names for these CSRs.
https://github.com/riscv/riscv-debug-spec/releases/tag/1.0



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