[all-commits] [llvm/llvm-project] 5f9499: [RISCV] isLoadFromStackSlot and isStoreToStackSlot...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f949924578c0314a1f7c3cfdd63b1ef8edb62ba
      https://github.com/llvm/llvm-project/commit/5f949924578c0314a1f7c3cfdd63b1ef8edb62ba
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-03-21 (Fri, 21 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/expandload.ll
    M llvm/test/CodeGen/RISCV/rvv/stack-slot-coloring.mir

  Log Message:
  -----------
  [RISCV] isLoadFromStackSlot and isStoreToStackSlot for vector spill/fill (#132296)

This is an adapted version of arsenm's
https://github.com/llvm/llvm-project/pull/120524.

The intention of the change is to enable dead stack slot copy
elimination in StackSlotColoring for vector loads and stores. In terms
of testing, see stack-slot-coloring.mir. This has little impact on in
tree tests otherwise.

This change has a different and smaller set of test diffs then then
@arsenm's patch because I'm using scalable sizes for the LMULs, not a
single signal value. His patch allowed vector load/store pairs of
different width to be deleted, mine does not. There's also simply been a
lot of churn in regalloc behavior on these particular tests recently, so
that may explain some of the diff as well.



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