[all-commits] [llvm/llvm-project] 5afa0f: [X86] Prevent APX NDD compression when it creates ...

[Daniel Zabawa via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5afa0fa9a6ba482cdc87945b71f5cd626b754d8f
      https://github.com/llvm/llvm-project/commit/5afa0fa9a6ba482cdc87945b71f5cd626b754d8f
  Author: Daniel Zabawa <daniel.zabawa at intel.com>
  Date:   2025-03-22 (Sat, 22 Mar 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86CompressEVEX.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    A llvm/test/CodeGen/X86/apx/ndd-false-deps-asm.mir
    A llvm/test/CodeGen/X86/apx/ndd-false-deps.mir

  Log Message:
  -----------
  [X86] Prevent APX NDD compression when it creates a partial write (#132051)

APX NDD instructions may be compressed when the result is also a source.
For 8/16b instructions, this may create partial register write hazards
if a previous super-register def is within the partial reg update
clearance, or incorrect code if the super-register is not dead.

This change prevents compression when the super-register is marked as an
implicit define, which the virtual rewriter already adds in the case
where a subregister is defined but the super-register is not dead.

The BreakFalseDeps interface is also updated to add implicit
super-register defs for NDD instructions that would incur partial-write
stalls if compressed to legacy ops.



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