[all-commits] [llvm/llvm-project] 7d742f: [libc++][test] Guard uses of `_LIBCPP_HAS_THREADS`...
ZhaoQi via All-commits
all-commits at lists.llvm.org
Fri Mar 21 00:16:29 PDT 2025
Branch: refs/heads/users/zhaoqi5/fix-tls-le-sym-type
Home: https://github.com/llvm/llvm-project
Commit: 7d742f97b035f8dd9adaeccb98a28d1b7586f343
https://github.com/llvm/llvm-project/commit/7d742f97b035f8dd9adaeccb98a28d1b7586f343
Author: S. B. Tam <cpplearner at outlook.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++][test] Guard uses of `_LIBCPP_HAS_THREADS` in FTM tests (#132258)
Commit: 4d5a963eaf6ad209487a321dee7f0cd2a0f98477
https://github.com/llvm/llvm-project/commit/4d5a963eaf6ad209487a321dee7f0cd2a0f98477
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VEMCInstLower.cpp
Log Message:
-----------
[VE] Rename VariantKind to Specifier and clean up code
Commit: c8a9a4109ac7756af3f0f5aab8c70e686a2f30b7
https://github.com/llvm/llvm-project/commit/c8a9a4109ac7756af3f0f5aab8c70e686a2f30b7
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/operation.py
Log Message:
-----------
[MLIR] [python] A few improvements to the Python bindings (#131686)
* `PyRegionList` is now sliceable. The dialect bindings generator seems
to assume it is sliceable already (!), yet accessing e.g. `cases` on
`scf.IndexedSwitchOp` raises a `TypeError` at runtime.
* `PyBlockList` and `PyOperationList` support negative indexing. It is
common for containers to do that in Python, and most container in the
MLIR Python bindings already allow the index to be negative.
Commit: aa4e6d846fceed9e0fe275f6486dc8ccee9caf0a
https://github.com/llvm/llvm-project/commit/aa4e6d846fceed9e0fe275f6486dc8ccee9caf0a
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.h
Log Message:
-----------
[Mips] Rename MipsExprKind to Specifier
Follow the X86 renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM’s usage, and fits the assembler's role seamlessly.
In addition, rename MipsMCExpr::getKind, which confusingly shadows the base class getKind.
Commit: c2692afc0a92cd5da140dfcdfff7818a5b8ce997
https://github.com/llvm/llvm-project/commit/c2692afc0a92cd5da140dfcdfff7818a5b8ce997
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCTargetStreamer.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
Log Message:
-----------
[PowerPC] Rename VariantKind to Specifier
Follow the X86 and Mips renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM’s usage, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
Commit: 13bb2f450ef9f64f393fe5527e5ac68362af8ccd
https://github.com/llvm/llvm-project/commit/13bb2f450ef9f64f393fe5527e5ac68362af8ccd
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
Log Message:
-----------
[MC] Rename some VariantKind functions to use Specifier
Use the more appropriate term "relocation specifier" and avoid the
variable name `Kind`, which conflicts with MCExpr and FixupKind.
Commit: 599005686a1c27ffe97bb4eb07fcd98359a2af99
https://github.com/llvm/llvm-project/commit/599005686a1c27ffe97bb4eb07fcd98359a2af99
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/IR/LegacyPassManager.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/lib/IR/SafepointIRVerifier.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/tools/llvm-exegesis/lib/Clustering.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
Log Message:
-----------
[llvm] Use *Set::insert_range (NFC) (#132325)
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently
gained C++23-style insert_range. This patch replaces:
Dest.insert(Src.begin(), Src.end());
with:
Dest.insert_range(Src);
This patch does not touch custom begin like succ_begin for now.
Commit: 3041fa6c7a3033040dce0933455be014760c6cb1
https://github.com/llvm/llvm-project/commit/3041fa6c7a3033040dce0933455be014760c6cb1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Analysis/TopologicalSortUtils.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/GPU/Utils/DistributionUtils.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/Location.cpp
M mlir/lib/Rewrite/FrozenRewritePatternSet.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/lib/Analysis/DataFlow/TestDenseDataFlowAnalysis.h
M mlir/test/lib/Analysis/DataFlow/TestSparseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Dialect/Linalg/TestLinalgElementwiseFusion.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir] Use *Set::insert_range (NFC) (#132326)
DenseSet, SmallPtrSet, SmallSet, SetVector, and StringSet recently
gained C++23-style insert_range. This patch replaces:
Dest.insert(Src.begin(), Src.end());
with:
Dest.insert_range(Src);
This patch does not touch custom begin like succ_begin for now.
Commit: 42a8813757dca4eed0ac462ed371f15b4ff004eb
https://github.com/llvm/llvm-project/commit/42a8813757dca4eed0ac462ed371f15b4ff004eb
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Log Message:
-----------
[RISCV] Rename VariantKind to Specifier
Follow the X86 and Mips renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
Commit: c9055e9780683735392ac0e74163020015eabf15
https://github.com/llvm/llvm-project/commit/c9055e9780683735392ac0e74163020015eabf15
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
Log Message:
-----------
[RISCV] Remove Specifier::VK_Invalid
Commit: 75c6fd3c8324d82daf713bcd1c6031dae64759f6
https://github.com/llvm/llvm-project/commit/75c6fd3c8324d82daf713bcd1c6031dae64759f6
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcMCInstLower.cpp
M llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp
Log Message:
-----------
[Sparc] Rename VariantKind to Specifier
Follow the X86, Mips, and RISCV renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
Commit: f5f6af8e7c0168327015717fc0b452f6152319af
https://github.com/llvm/llvm-project/commit/f5f6af8e7c0168327015717fc0b452f6152319af
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
A llvm/test/CodeGen/AArch64/cond-br-tuning-instr-ref.mir
Log Message:
-----------
[InstrRef] Preserve debug instr num in aarch64-cond-br-tuning. (#132081)
The aarch64-cond-br-tuning pass transforms a CBZX instruction into a
conditional branch (B.cond). One of the by products of the
transformation is that the source instruction of the CBZX, which is an
ANDXri instruction, gets transformed into a ANDSXri instruction, however
this transformation doesn't preserve it's debug instruction number.
This patch fixes that issue.
Commit: 910f7f45f27d1f3cfad779669d0e0f15ff5b9686
https://github.com/llvm/llvm-project/commit/910f7f45f27d1f3cfad779669d0e0f15ff5b9686
Author: Brad Smith <brad at comstyle.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Haiku.h
Log Message:
-----------
[Driver] Haiku address sanitizer support (#132335)
Co-authored-by: Jérôme Duval <jerome.duval at gmail.com>
Commit: 111cc472d1297386bc3220659d3faec2c29795cf
https://github.com/llvm/llvm-project/commit/111cc472d1297386bc3220659d3faec2c29795cf
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
Log Message:
-----------
[AVR] Rename VariantKind to Specifier
Follow the X86, Mips, and RISCV renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
Commit: ad0827d364293a42540885ae41b78995e2818581
https://github.com/llvm/llvm-project/commit/ad0827d364293a42540885ae41b78995e2818581
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M llvm/test/Transforms/GVN/assume.ll
M llvm/test/Transforms/GVN/basic.ll
M llvm/test/Transforms/GVN/nonescaping.ll
M llvm/test/Transforms/GVN/pr14166.ll
Log Message:
-----------
[GVN] Add MemorySSA checks in tests 1/N (#130261)
Add MemorySSA checks in some GVN tests. This is first patch of the series and many more might come based on tests pass/fail.
Commit: 1667a2afd86ffbfc376cb2550205abf0f1a4f064
https://github.com/llvm/llvm-project/commit/1667a2afd86ffbfc376cb2550205abf0f1a4f064
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
Log Message:
-----------
[clang][ExprConst] Check record base classes for valid structs (#132270)
In error cases, the base might be None.
Fixes https://github.com/llvm/llvm-project/issues/132257
Commit: 2089b081ff2b8acb50bc0b9da7a3cf44387d797e
https://github.com/llvm/llvm-project/commit/2089b081ff2b8acb50bc0b9da7a3cf44387d797e
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
Log Message:
-----------
[ARM] Rename VariantKind to Specifier
Follow the X86, Mips, and RISCV renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
Commit: 103119a435c9cd1c73da92758a503abee1bac3da
https://github.com/llvm/llvm-project/commit/103119a435c9cd1c73da92758a503abee1bac3da
Author: Sam Parker <sam.parker at arm.com>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
A llvm/test/CodeGen/WebAssembly/wide-simd-mul.ll
Log Message:
-----------
[WebAssembly] Lower wide SIMD i8 muls (#130785)
Currently, 'wide' i32 simd multiplication, with extended i8 elements,
will perform the multiplication with i32 So, for IR like the following:
```
%wide.a = sext <8 x i8> %a to <8 x i32>
%wide.b = sext <8 x i8> %a to <8 x i32>
%mul = mul <8 x i32> %wide.a, %wide.b
ret <8 x i32> %mul
```
We would generate the following sequence:
```
i16x8.extend_low_i8x16_s $push6=, $1
local.tee $push5=, $3=, $pop6
i32x4.extmul_low_i16x8_s $push0=, $pop5, $3
v128.store 0($0), $pop0
i8x16.shuffle $push1=, $1, $1, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
i16x8.extend_low_i8x16_s $push4=, $pop1
local.tee $push3=, $1=, $pop4
i32x4.extmul_low_i16x8_s $push2=, $pop3, $1
v128.store 16($0), $pop2
return
```
But now we perform the multiplication with i16, resulting in:
```
i16x8.extmul_low_i8x16_s $push3=, $1, $1
local.tee $push2=, $1=, $pop3
i32x4.extend_high_i16x8_s $push0=, $pop2
v128.store 16($0), $pop0
i32x4.extend_low_i16x8_s $push1=, $1
v128.store 0($0), $pop1
return
```
Commit: 058a4e8170f2c66764b78c88e574d5c364c6bd93
https://github.com/llvm/llvm-project/commit/058a4e8170f2c66764b78c88e574d5c364c6bd93
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
Log Message:
-----------
[LoongArch] Rename VariantKind to Specifier
Follow the X86, Mips, and RISCV renaming.
> "Relocation modifier" suggests adjustments happen during the linker's relocation step rather than the assembler's expression evaluation.
> "Relocation specifier" is clear, aligns with Arm and IBM AIX's documentation, and fits the assembler's role seamlessly.
In addition, rename *MCExpr::getKind, which confusingly shadows the base class getKind.
The parseSpecifier name follows Sparc.
Commit: dcaaecd3a307ed4a67c19a1ed2df543bf4b1bb21
https://github.com/llvm/llvm-project/commit/dcaaecd3a307ed4a67c19a1ed2df543bf4b1bb21
Author: Qi Zhao <zhaoqi01 at loongson.cn>
Date: 2025-03-21 (Fri, 21 Mar 2025)
Changed paths:
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Haiku.h
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/IR/LegacyPassManager.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/lib/IR/SafepointIRVerifier.cpp
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsMCInstLower.h
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCTargetStreamer.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcMCInstLower.cpp
M llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VEMCInstLower.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
A llvm/test/CodeGen/AArch64/cond-br-tuning-instr-ref.mir
A llvm/test/CodeGen/WebAssembly/wide-simd-mul.ll
M llvm/test/Transforms/GVN/assume.ll
M llvm/test/Transforms/GVN/basic.ll
M llvm/test/Transforms/GVN/nonescaping.ll
M llvm/test/Transforms/GVN/pr14166.ll
M llvm/tools/llvm-exegesis/lib/Clustering.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profgen/ProfiledBinary.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Analysis/TopologicalSortUtils.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/GPU/Utils/DistributionUtils.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/Location.cpp
M mlir/lib/Rewrite/FrozenRewritePatternSet.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/lib/Analysis/DataFlow/TestDenseDataFlowAnalysis.h
M mlir/test/lib/Analysis/DataFlow/TestSparseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Dialect/Linalg/TestLinalgElementwiseFusion.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/python/ir/operation.py
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
Merge remote-tracking branch 'upstream/main' into users/zhaoqi5/fix-tls-le-sym-type
Compare: https://github.com/llvm/llvm-project/compare/161d4d31ba8f...dcaaecd3a307
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