[all-commits] [llvm/llvm-project] 3e6f61: [llvm][ADT] Add `getSingleElement` helper (#131508)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Mar 19 10:21:48 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpnfc-redesign-schedule-bundle-separate-from-schedule-data-nfc
Home: https://github.com/llvm/llvm-project
Commit: 3e6f618e86f5fbad2c2d5802416ec3d3366a2837
https://github.com/llvm/llvm-project/commit/3e6f618e86f5fbad2c2d5802416ec3d3366a2837
Author: Matthias Springer <me at m-sp.org>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
M llvm/unittests/ADT/STLExtrasTest.cpp
Log Message:
-----------
[llvm][ADT] Add `getSingleElement` helper (#131508)
This commit adds a new helper function: `getSingleElement`
This function asserts that the container has a single element and then
returns that element. This helper function is useful during 1:N dialect
conversions in MLIR, where certain `ValueRange`s (returned from the
adaptor) are known to have a single value.
Commit: 950bc6cd77455b1ec1679cf9f125055e2de1910f
https://github.com/llvm/llvm-project/commit/950bc6cd77455b1ec1679cf9f125055e2de1910f
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
Log Message:
-----------
[LoopFuse] Change placeholder from `undef` to `poison` (#131535)
Use `poison` instead of `undef` as a placeholder for phi entries of
unreachable predecessors.
Commit: 91328dbae986dfa93cf2acef0a93361fd5ced66d
https://github.com/llvm/llvm-project/commit/91328dbae986dfa93cf2acef0a93361fd5ced66d
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate user-defined conversion functions (#131434)
Also fix/delete existing invalid/redundant test cases.
Fix #130894
Commit: 81ba006296680c9d62aba12c5e3f083e2f7c595d
https://github.com/llvm/llvm-project/commit/81ba006296680c9d62aba12c5e3f083e2f7c595d
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/X86/nocf_check.ll
Log Message:
-----------
[X86] nocf_check: disable tail call
When a function pointer is annotated with
`void (*fptr)(void) __attribute__((nocf_check));`, calling it should use
the NOTRACK prefix, as the callee may not contain an ENDBR.
https://reviews.llvm.org/D41879 implemented NOTRACK variants for
X86ISD::CALL and ISD::BRIND but not for TCRETURN. Given that there are
so many tail call variants (e.g. conditional tailcall
https://reviews.llvm.org/D29856), let's just disable tailcall.
While nocf_check has some uses within the Linux kernel, it isn't a
popular attribute.
Fix #91228
Pull Request: https://github.com/llvm/llvm-project/pull/131487
Commit: 2dc123b33d51fcccb9e1af7230bc6573f77b3ccc
https://github.com/llvm/llvm-project/commit/2dc123b33d51fcccb9e1af7230bc6573f77b3ccc
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
M clang/test/SemaOpenCL/invalid-kernel-attrs.cl
Log Message:
-----------
[clang][opencl] Allow passing all zeros to reqd_work_group_size (#131543)
Allow passing all zeros to reqd_work_group_size.
Test plan: ninja check-all
Commit: 125c4db7301875cae928406043f02ed5b1133195
https://github.com/llvm/llvm-project/commit/125c4db7301875cae928406043f02ed5b1133195
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/tools/lldb-dap/Handler/SetVariableRequestHandler.cpp
Log Message:
-----------
[lldb][lldb-dap] setVariable request should send the correct response (#130773)
The display value was incorrectly sent as "result" instead of "value".
Commit: 2e78abe788c55721033d38a408d8f34af20bc8cc
https://github.com/llvm/llvm-project/commit/2e78abe788c55721033d38a408d8f34af20bc8cc
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp
Log Message:
-----------
[MSP430] Delete unneeded fixupNeedsRelaxationAdvanced
Commit: 4b86a7f3860a3cb0368e308494f65c103c02fa18
https://github.com/llvm/llvm-project/commit/4b86a7f3860a3cb0368e308494f65c103c02fa18
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M clang/tools/clang-format/git-clang-format
Log Message:
-----------
[clang-format] Update the minimum python version requirement
See https://llvm.org/docs/GettingStarted.html#software
Fix #131456
Commit: 4fde8c341f9166e6ec6dff6e7704be175e382f5b
https://github.com/llvm/llvm-project/commit/4fde8c341f9166e6ec6dff6e7704be175e382f5b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
A flang/test/Lower/CUDA/cuda-shared.cuf
Log Message:
-----------
[flang][cuda] Lower CUDA shared variable with cuf.shared_memory op (#131399)
Use `cuf.shared_memory` operation instead of `cuf.alloc` for CUDA shared
variable. These variables do not need free operations.
Commit: e24e523150c2a4e7597dae9919da0378ee3d4255
https://github.com/llvm/llvm-project/commit/e24e523150c2a4e7597dae9919da0378ee3d4255
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
Log Message:
-----------
[LoopVectorize] Add test for follow-up metadata for loops (NFC) (#131337)
When pragma of loop transformations are encoded in LLVM IR, follow-up
metadata is used if multiple transformations are specified. They are
used to explicitly express the order of the transformations. However,
they are not properly processed on each transformation pass, so now only
the first one is attempted to be applied. This is a pre-commit to add a
test that causes the problem.
ref:
https://github.com/llvm/llvm-project/pull/127474#issuecomment-2717790398
Commit: 752aa81c4ff754945c695ac771577c1370564411
https://github.com/llvm/llvm-project/commit/752aa81c4ff754945c695ac771577c1370564411
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[clang][RISCV] Rename variable name in SemaRISCV. NFC (#131261)
Commit: 2a2d6d61b178f0d8d542333155510896c7bc75b5
https://github.com/llvm/llvm-project/commit/2a2d6d61b178f0d8d542333155510896c7bc75b5
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
Log Message:
-----------
[RISCV] Remove unused check prefixes from half arith strict test. NFC
Commit: 687c9d359ee124acecbdcdd699aefa77ccd6d16a
https://github.com/llvm/llvm-project/commit/687c9d359ee124acecbdcdd699aefa77ccd6d16a
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/FEntryInserter.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/FEntryInserter.cpp
M llvm/lib/Passes/PassBuilder.cpp
A llvm/test/CodeGen/X86/fentry.mir
Log Message:
-----------
[CodeGen][NPM] Port FEntryInserter to NPM (#129857)
Commit: de60c0e034f90b634235ce01fc19da9afd8b699c
https://github.com/llvm/llvm-project/commit/de60c0e034f90b634235ce01fc19da9afd8b699c
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Log Message:
-----------
[MC] .reloc: move FirstLiteralRelocationKind check to evaluateFixup
Target shouldForceRelocation checks `FirstLiteralRelocationKind` to
determine whether a relocation is forced due to the .reloc directive. We
should move the code to evaluateFixup so that many targets don't need to
override shouldForceRelocation.
Commit: baab447aadd59b34bd838584b16d11475329853f
https://github.com/llvm/llvm-project/commit/baab447aadd59b34bd838584b16d11475329853f
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/tools/llc/new-pm/option-conflict.ll
M llvm/tools/llc/NewPMDriver.cpp
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Report error in lieu of warning for invalid cl option (#128846)
Commit: c5a491e9ea22014b65664b6e09134b4f055933e2
https://github.com/llvm/llvm-project/commit/c5a491e9ea22014b65664b6e09134b4f055933e2
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
A llvm/test/Transforms/LoopUnroll/pr131465.ll
Log Message:
-----------
[SCEV] Check whether the start is non-zero in `ScalarEvolution::howFarToZero` (#131522)
https://github.com/llvm/llvm-project/pull/94525 assumes that the loop
will be infinite when the stride is zero. However, it doesn't hold when
the start value of addrec is also zero.
Closes https://github.com/llvm/llvm-project/issues/131465.
Commit: e0fee65b87872c434ab7a60fe237573d5ce88ca9
https://github.com/llvm/llvm-project/commit/e0fee65b87872c434ab7a60fe237573d5ce88ca9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
Log Message:
-----------
[PowerPC] Use Register in FastISel. NFC
Commit: b09b9ac1081d19c8021df8e55e96cd1325f0eed0
https://github.com/llvm/llvm-project/commit/b09b9ac1081d19c8021df8e55e96cd1325f0eed0
Author: Hua Tian <akiratian at tencent.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ModuloSchedule.h
M llvm/lib/CodeGen/ModuloSchedule.cpp
A llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-issue128714.mir
Log Message:
-----------
[llvm][CodeGen] Fix the empty interval issue in Window Scheduler (#129204)
The interval of newly generated reg in ModuloScheduleExpander is empty.
This will cause crash at some corner case. This patch recalculate the
live intervals of these regs.
Commit: 8a1b4d0ed2bb5cf29714cef33604b53f42ae8273
https://github.com/llvm/llvm-project/commit/8a1b4d0ed2bb5cf29714cef33604b53f42ae8273
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
Log Message:
-----------
[MC] Rework AVR #121498 to not add extra argument to shouldForceRelocation
This removes the extra argument from commit 814b34f31e163e76b816194004689985f5b9fd7b.
Also remove unneeded `>= FirstLiteralRelocationKind`.
Commit: f75d75b8899aa44cfb2cd4e94fb43fa561f0f285
https://github.com/llvm/llvm-project/commit/f75d75b8899aa44cfb2cd4e94fb43fa561f0f285
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
Log Message:
-----------
AMDGPU: Use MFPropsModifier modifier in SIFoldOperands (#127752)
This doesn't appear to work. I do not get an error in the new PM.
---------
Co-authored-by: Akshat Oke <Akshat.Oke at amd.com>
Commit: f402953339fa5b1c206cb5d6ac3d9b15b1e81509
https://github.com/llvm/llvm-project/commit/f402953339fa5b1c206cb5d6ac3d9b15b1e81509
Author: Lang Hames <lhames at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/WrapperFunctionUtils.h
Log Message:
-----------
[ORC] Fix code example in comment: SPS function sigs are function types. NFCI.
Commit: 6c867e27a7b597910571677abdef77b703a5a601
https://github.com/llvm/llvm-project/commit/6c867e27a7b597910571677abdef77b703a5a601
Author: Matthias Springer <me at m-sp.org>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/CommonFolders.h
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp
M mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Linalg/Transforms/SubsetInsertionOpInterfaceImpl.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Quant/Transforms/StripFuncQuantTypes.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseIterationToScf.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Tools/PDLL/CodeGen/MLIRGen.cpp
M mlir/test/lib/Analysis/TestCFGLoopInfo.cpp
Log Message:
-----------
[mlir] Use `getSingleElement`/`hasSingleElement` in various places (#131460)
This is a code cleanup. Update a few places in MLIR that should use
`hasSingleElement`/`getSingleElement`.
Note: `hasSingleElement` is faster than `.getSize() == 1` when it is
used with linked lists etc.
Depends on #131508.
Commit: 009d36222cfdb59f49597e01d157ca4f65ac9295
https://github.com/llvm/llvm-project/commit/009d36222cfdb59f49597e01d157ca4f65ac9295
Author: Letu Ren <fantasquex at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Sema/SemaCodeCompletion.h
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
A clang/test/CodeCompletion/if-const.cpp
Log Message:
-----------
[clang][CodeComplete] Add code completion for if constexpr and consteval (#124315)
Code complete `constexpr` and `consteval` keywords after `if` in the
relevant language modes. If pattern completion is enabled, the
completions also include placeholders for the condition (in the case
of `constexpr`) and statement block.
Commit: 2c35cb6f16b21d984b298e2ddf445d20f194e142
https://github.com/llvm/llvm-project/commit/2c35cb6f16b21d984b298e2ddf445d20f194e142
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
M llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
Log Message:
-----------
[MC] Remove unneeded getNumFixupKinds
Commit: 05607a3f39f97449e75358159ce8526e5d734615
https://github.com/llvm/llvm-project/commit/05607a3f39f97449e75358159ce8526e5d734615
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#131551)
Commit: 78408fddccf34b7d79eb655fa2cb4dfacdfb8ae3
https://github.com/llvm/llvm-project/commit/78408fddccf34b7d79eb655fa2cb4dfacdfb8ae3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
Log Message:
-----------
[ExecutionEngine] Avoid repeated map lookups (NFC) (#131552)
Commit: 7eb8b731784722669106267764c74997e9a63cbe
https://github.com/llvm/llvm-project/commit/7eb8b731784722669106267764c74997e9a63cbe
Author: sharang.12492 <sharang.12492 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Semantics/OpenMP/test_taskloop_lastprivate_semantic_restrictions.f90
A flang/test/Semantics/OpenMP/test_taskloop_reduction_semantic_restrictions.f90
Log Message:
-----------
[Flang][OpenMP][taskloop] Adding missing semantic checks in Taskloop (#128431)
Below semantic checks for Taskloop clause mentioned in OpenMP [5.2]
specification were missing, this patch contains the semantic checks,
corresponding error messages and test cases:
OpenMP standard [5.2]:
[12.6] Taskloop Construct
[Restrictions]
Restrictions to the taskloop construct are as follows:
• The reduction-modifier must be default.
• The conditional lastprivate-modifier must not be specified.
Authored-by: shkaushi <sharang.kaushik at amd.com>
Commit: 3b1e18c2dba850922bc259a258e65490058e523d
https://github.com/llvm/llvm-project/commit/3b1e18c2dba850922bc259a258e65490058e523d
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/CapturingThisInMemberVariableCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/CapturingThisInMemberVariableCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/capturing-this-in-member-variable.cpp
Log Message:
-----------
[clang-tidy] Add new check bugprone-capture-this-by-field (#130297)
Finds lambda captures that capture the ``this`` pointer and store it as
class
members without handle the copy and move constructors and the
assignments.
Capture this in a lambda and store it as a class member is dangerous
because the
lambda can outlive the object it captures. Especially when the object is
copied
or moved, the captured ``this`` pointer will be implicitly propagated to
the
new object. Most of the time, people will believe that the captured
``this``
pointer points to the new object, which will lead to bugs.
Fixes: #120863
---------
Co-authored-by: Baranov Victor <70346889+vbvictor at users.noreply.github.com>
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: c3f6d2c024968d21157aa0a523ef1f1e61a07441
https://github.com/llvm/llvm-project/commit/c3f6d2c024968d21157aa0a523ef1f1e61a07441
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
Log Message:
-----------
[gn build] Port 3b1e18c2dba8
Commit: 57e36419b251f7e5a86566c86b4d61fbd605db5c
https://github.com/llvm/llvm-project/commit/57e36419b251f7e5a86566c86b4d61fbd605db5c
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/Statistics.rst
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
A clang/include/clang/StaticAnalyzer/Core/PathSensitive/EntryPointStats.h
M clang/lib/StaticAnalyzer/Checkers/AnalyzerStatsChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/CMakeLists.txt
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
A clang/lib/StaticAnalyzer/Core/EntryPointStats.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/lib/StaticAnalyzer/Core/WorkList.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/test/Analysis/analyzer-config.c
A clang/test/Analysis/analyzer-stats/entry-point-stats.cpp
A clang/test/Analysis/csv2json.py
M clang/test/lit.cfg.py
Log Message:
-----------
[analyzer] Introduce per-entry-point statistics (#131175)
So far CSA was relying on the LLVM Statistic package that allowed us to
gather some data about analysis of an entire translation unit. However,
the translation unit consists of a collection of loosely related entry
points. Aggregating data across multiple such entry points is often
counter productive.
This change introduces a new lightweight always-on facility to collect
Boolean or numerical statistics for each entry point and dump them in a
CSV format. Such format makes it easy to aggregate data across multiple
translation units and analyze it with common data-processing tools.
We break down the existing statistics that were collected on the per-TU
basis into values per entry point.
Additionally, we enable the statistics unconditionally (STATISTIC ->
ALWAYS_ENABLED_STATISTIC) to facilitate their use (you can gather the
data with a simple run-time flag rather than having to recompile the
analyzer). These statistics are very light and add virtually no
overhead.
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
CPP-6160
Commit: 9b1ce477af5603e665258362fb8b9fe4091efbde
https://github.com/llvm/llvm-project/commit/9b1ce477af5603e665258362fb8b9fe4091efbde
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Core/BUILD.gn
Log Message:
-----------
[gn build] Port 57e36419b251
Commit: ccfabe8380572d99a6833bfff09a62018aca1a15
https://github.com/llvm/llvm-project/commit/ccfabe8380572d99a6833bfff09a62018aca1a15
Author: Julian Ruess <julianonline+github at posteo.de>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tidy-diff] Add an option to treat warnings as errors (#128221)
This patch allows to treat warnings as erros using clang-tidy-diff.
Co-authored-by: Piotr Zegar <me at piotrzegar.pl>
Commit: 3af6c9fa832ac29125cad76acb397d6235c371e9
https://github.com/llvm/llvm-project/commit/3af6c9fa832ac29125cad76acb397d6235c371e9
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M lldb/tools/lldb-dap/Transport.cpp
Log Message:
-----------
[lldb][lldb-dap][NFC] Fix swapped logging directions for DAP messages. (#131544)
The logging markers for incoming ("<--") and outgoing ("-->") messages
were incorrectly reversed. from #7790d69
Commit: 6b47bba44087caa7d4805bdb3229153a3bfba7a5
https://github.com/llvm/llvm-project/commit/6b47bba44087caa7d4805bdb3229153a3bfba7a5
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
Log Message:
-----------
[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
New intrinsics / instructions :
int_amdgcn_ds_bvh_stack_push4_pop1_rtn / ds_bvh_stack_push4_pop1_rtn_b32
int_amdgcn_ds_bvh_stack_push8_pop1_rtn / ds_bvh_stack_push8_pop1_rtn_b32
int_amdgcn_ds_bvh_stack_push8_pop2_rtn / ds_bvh_stack_push8_pop2_rtn_b64
Co-authored-by: Mateja Marjanovic <mateja.marjanovic at amd.com>
Commit: fd41f1b0ce1e7d4eb2d51da82418b3e41dbb59ba
https://github.com/llvm/llvm-project/commit/fd41f1b0ce1e7d4eb2d51da82418b3e41dbb59ba
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
A clang/test/Analysis/fixed-address-notes.c
Log Message:
-----------
[clang][analyzer] Add BugReporterVisitor messages for non-null fixed pointer (#129557)
Commit: a10e1e0135970861d3fd2f742e3628fe94e00af4
https://github.com/llvm/llvm-project/commit/a10e1e0135970861d3fd2f742e3628fe94e00af4
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
Log Message:
-----------
[RISCV] Remove unused check prefixes from double maximum/minimum test. NFC
Commit: d9110858ee938db424887cd3435488525dd632cb
https://github.com/llvm/llvm-project/commit/d9110858ee938db424887cd3435488525dd632cb
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Sema/SemaAccess.cpp
M clang/test/SemaCXX/concept-crash-on-diagnostic.cpp
Log Message:
-----------
[Clang] Fix an incorrect assumption on getTemplatedDecl() (#131559)
Since a68d20e98, we've been calling HandleDelayedAccessCheck() for
concept declarations when the declaration contains invalid member
accesses.
However, a concept declaration is TemplateDecl such that doesn't contain
any TemplatedDecl.
Fixes https://github.com/llvm/llvm-project/issues/131530
Commit: 8cc6c2e80fb007f0e0e2ee65bca070c0f7fb7010
https://github.com/llvm/llvm-project/commit/8cc6c2e80fb007f0e0e2ee65bca070c0f7fb7010
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
Log Message:
-----------
AMDGPU: Migrate more tests away from undef (#131314)
andorbitset.ll is interesting since it directly depends on the
difference between poison and undef. Not sure it's useful to keep
the version using poison, I assume none of this code makes it to
codegen.
si-spill-cf.ll was also a nasty case, which I doubt has been reproducing
its original issue for a very long time. I had to reclaim an older version,
replace some of the poison uses, and run simplify-cfg. There's a very
slight change in the final CFG with this, but final the output is approximately
the same as it used to be.
Commit: 4f2ee07454b0d0b156a728ca540f584310ef4a62
https://github.com/llvm/llvm-project/commit/4f2ee07454b0d0b156a728ca540f584310ef4a62
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/test/AArch64/test-indirect-branch.s
Log Message:
-----------
[BOLT][AArch64] Do not crash on authenticated branch instructions (#129898)
When an indirect branch instruction is decoded, analyzeIndirectBranch
method is asked if this is a well-known code pattern. On AArch64, the
only special pattern which is detected is Jump Table, emitted as a
branch to the sum of a constant base address and a variable offset.
Therefore, `Inst.getOpcode()` being one of `AArch64::BRA*` means Inst
cannot belong to such Jump Table pattern, thus returning early.
Commit: ee8a804cbab56fdc00dea43091e2cfabd01a3b9f
https://github.com/llvm/llvm-project/commit/ee8a804cbab56fdc00dea43091e2cfabd01a3b9f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
Log Message:
-----------
AMDGPU: Switch test to generated checks (#131315)
I doubt this is testing what it originally intended anymore. Also
replace an undef.
Commit: a6ae965cec96ac3a79b908afa9e2cd1ed5f3d5e1
https://github.com/llvm/llvm-project/commit/a6ae965cec96ac3a79b908afa9e2cd1ed5f3d5e1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
Log Message:
-----------
AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (#131316)
Also remove unnecessarily requiring asserts, and replace undef
with poison.
Commit: 1f1f8200bdf568ce41259ffcf78b32dd4630e1e8
https://github.com/llvm/llvm-project/commit/1f1f8200bdf568ce41259ffcf78b32dd4630e1e8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
Log Message:
-----------
AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (#131317)
This just checked the s_endpgm. Generate full checks, and remove undefs.
Commit: 7dcea28bf92e49737fa285e93621cfa814323524
https://github.com/llvm/llvm-project/commit/7dcea28bf92e49737fa285e93621cfa814323524
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
Log Message:
-----------
[AMDGPU] Add identity_combines to RegBankCombiner (#131305)
Commit: 27099982da2f5a6c2d282d6b385e79d080669546
https://github.com/llvm/llvm-project/commit/27099982da2f5a6c2d282d6b385e79d080669546
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugType.h
M clang/include/clang/StaticAnalyzer/Core/Checker.h
M clang/include/clang/StaticAnalyzer/Core/CheckerManager.h
M clang/lib/StaticAnalyzer/Checkers/DivZeroChecker.cpp
M clang/lib/StaticAnalyzer/Core/Checker.cpp
Log Message:
-----------
[NFC][analyzer] Framework for multipart checkers (#130985)
In the static analyzer codebase we have a traditional pattern where a
single checker class (and its singleton instance) acts as the
implementation of several (user-facing or modeling) checkers that have
shared state and logic, but have their own names and can be enabled or
disabled separately.
Currently these multipart checker classes all reimplement the same
boilerplate logic to store the enabled/disabled state, the name and the
bug types associated with the checker parts. This commit extends
`CheckerBase`, `BugType` and the checker registration process to offer
an easy-to-use alternative to that boilerplate (which includes the ugly
lazy initialization of `mutable std::unique_ptr<BugType>`s).
In this new framework the single-part checkers are internally
represented as "multipart checkers with just one part" (because this way
I don't need to reimplement the same logic twice) but this does not
require any changes in the code of simple single-part checkers.
I do not claim that these multi-part checkers are perfect from an
architectural point of view; but they won't suddenly disappear after
many years of existence, so we might as well introduce a clear framework
for them. (Switching to e.g. 1:1 correspondence between checker classes
and checker names would be a prohibitively complex change.)
This PR ports `DivZeroChecker` to the new framework as a proof of
concept. I'm planning to do a series of follow-up commits to port the
rest of the multi-part checker.
Commit: ab1dcac6db2229387c711b7a4059e36ba09583cc
https://github.com/llvm/llvm-project/commit/ab1dcac6db2229387c711b7a4059e36ba09583cc
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
Log Message:
-----------
[AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (#131306)
See #64591
Commit: e456579e346c0790603544dc7617edfe44953f4c
https://github.com/llvm/llvm-project/commit/e456579e346c0790603544dc7617edfe44953f4c
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
Log Message:
-----------
[AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (#131307)
We can add a bunch of exts/truncs during RBSelect, we should be able to fold
them away afterwards.
Commit: 0878dd14b20579dd127396787ec81ba7239b3366
https://github.com/llvm/llvm-project/commit/0878dd14b20579dd127396787ec81ba7239b3366
Author: David Green <david.green at arm.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
Log Message:
-----------
[AArch64][GlobalISel] Add coverage for arm64-neon-2velem.ll. NFC
Commit: 93e0df07c2b32610ff8cc9451b5b5036f9a3ed37
https://github.com/llvm/llvm-project/commit/93e0df07c2b32610ff8cc9451b5b5036f9a3ed37
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/metadirective-common.f90
Log Message:
-----------
[Flang][OpenMP] Allow zero trait score (#131473)
Commit: 5c73c5c9bf0e048737682040f22734c3eb63cbbf
https://github.com/llvm/llvm-project/commit/5c73c5c9bf0e048737682040f22734c3eb63cbbf
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (#131576)
Commit: 0c34d7a9e7a4b5d249dda46ff8ab754cf3f934c7
https://github.com/llvm/llvm-project/commit/0c34d7a9e7a4b5d249dda46ff8ab754cf3f934c7
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa] Require operand/result tensors of at least rank 1 for some operations (#131335)
This commit updates the following operations (operands/results) to be of
at least rank 1 such that it aligns with the expectations of the
specification:
- ARGMAX (input)
- REDUCE_ALL (input/output)
- REDUCE_ANY (input/output)
- REDUCE_MAX (input/output)
- REDUCE_MIN (input/output)
- REDUCE_PRODUCT (input/output)
- REDUCE_SUM (input/output)
- CONCAT (each input in input1/output)
- PAD (input1/output)
- REVERSE (input1/output)
- SLICE (input1/output)
- TILE (input1/output)
- TRANSPOSE (input1/output)
In addition to this change, PAD has been updated to allow unranked
tensors for input1/output, inline with other operations.
Commit: 846cf86b2bbec68c01f762f65e2778a32fe15daa
https://github.com/llvm/llvm-project/commit/846cf86b2bbec68c01f762f65e2778a32fe15daa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
libclc: Add missing gfx950 target (#131585)
Commit: 8c939f54b4907935a877e75d09ee88bf90401cb4
https://github.com/llvm/llvm-project/commit/8c939f54b4907935a877e75d09ee88bf90401cb4
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Log Message:
-----------
[WebAssembly] Change placeholder from `undef` to `poison` (#131536)
Use `poison` instead of `undef` as a placeholder for phi entries of
unreachable predecessors.
Commit: 6eb32a2fa0d16bea03f22dd2078f53da6d9352cd
https://github.com/llvm/llvm-project/commit/6eb32a2fa0d16bea03f22dd2078f53da6d9352cd
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGException.cpp
Log Message:
-----------
[clang] Change placeholder from `undef` to `poison` (#131533)
Return a `poison` value, instead of `undef`, if there is no available
SEH info.
Commit: e57cd100ca297cf81854e35cccbf703edddd4aad
https://github.com/llvm/llvm-project/commit/e57cd100ca297cf81854e35cccbf703edddd4aad
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Support/Compiler.h
M llvm/include/llvm/Support/Compiler.h
Log Message:
-----------
Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (#131578)
While building llvm (clang, lld) against emscripten we see this
[error](https://github.com/emscripten-forge/recipes/actions/runs/13803029307/job/38608794602#step:9:1715)
```
│ │ In file included from $SRC_DIR/llvm/lib/Frontend/OpenACC/ACC.cpp:9:
│ │ $SRC_DIR/build/include/llvm/Frontend/OpenACC/ACC.h.inc:192:1: error: unknown type name 'LLVM_ABI'
│ │ 192 | LLVM_ABI Directive getOpenACCDirectiveKind(llvm::StringRef Str);
│ │ | ^
│ │ $SRC_DIR/build/include/llvm/Frontend/OpenACC/ACC.h.inc:192:19: error: expected ';' after top level declarator
│ │ 192 | LLVM_ABI Directive getOpenACCDirectiveKind(llvm::StringRef Str);
│ │ | ^
```
Now this was happening because we weren't defining LLVM_ABI correctly when building against emscripten. If you see [llvm/Support/Compiler.h](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/Compiler.h#L206-L210), the condition only checked for the platform __WASM__ . Now Emscripten targets WebAssembly but doesn't imply the platform by default so the check isn't complete to define LLVM_ABI.
The successful build after using this patch can be seen [here](https://github.com/emscripten-forge/recipes/actions/runs/13805214092/job/38614585621)
Commit: f4feab927ba33e897c4f05bf3b52226bc0a824c7
https://github.com/llvm/llvm-project/commit/f4feab927ba33e897c4f05bf3b52226bc0a824c7
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[NFC][KeyInstr] Add (LLVM_)EXPERIMENTAL_KEY_INSTRUCTIONS (cmake/)definition (#131344)
Key Instructions will start development behind a compile time flag to avoid
passing on the increased memory usage to all debug builds. We're working on
improving DILocation memory characteristics simultaneously; once that work lands
we can remove `EXPERIMENTAL_KEY_INSTRUCTIONS`.
This patch doesn't add any code, it's just so we can get the SIE buildbot
building with the new option right away.
Commit: 6085f3f6a80dc3be97d31a4c31a22fd77dbb6e83
https://github.com/llvm/llvm-project/commit/6085f3f6a80dc3be97d31a4c31a22fd77dbb6e83
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M openmp/runtime/src/kmp_sched.cpp
Log Message:
-----------
[OpenMP] Address __kmp_dist_for_static_init issue (#129902)
This patch attempts to provide a fix for an issue that appears when the
`__kmp_dist_for_static_init` function is called from a serialized team.
This is triggered by code generated by flang for `distribute parallel
do` constructs whenever an `if` clause for the `parallel` leaf construct
is present. This results in the introduction of a call to
`__kmpc_fork_call_if` in place of `__kmpc_fork_call`. When it evaluates
to `false`, it defers execution to `__kmp_serialized_parallel`, which
creates a new serial team that is picked up by
`__kmp_dist_for_static_init`, resulting in an incorrect `team` pointer
that causes the `nteams == (kmp_uint32)team->t.t_parent->t.t_nproc`
assertion to fail.
The sequence of calls replicating this issue can be summarized as:
- `__kmpc_fork_teams`
- `__kmpc_fork_call_if`
- `__kmpc_dist_for_static_init_*`
Since I am not familiar with the implementation of the OpenMP runtime,
it is possible that the above sequence of calls is incorrect, or that
the bug can be better fixed in another way, so I am open to discussing
this.
The following Fortran program can be compiled with flang to show the
issue:
```f90
! Compile and run: flang -fopenmp test.f90 -o test && ./test
! Check LLVM IR: flang -fc1 -emit-llvm -fopenmp test.f90 -o -
program main
implicit none
integer, parameter :: n = 10
integer :: i, idx(n)
!$omp teams
!$omp distribute parallel do if(.false.)
do i=1,n
idx(i) = i
end do
!$omp end teams
print *, idx
end program
```
Commit: e0223fa24aedf14895ea31beb87dac6d5a2137f0
https://github.com/llvm/llvm-project/commit/e0223fa24aedf14895ea31beb87dac6d5a2137f0
Author: Imad Aldij <os at imadij.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
Log Message:
-----------
[Clang][NFC] Rename SecondArgIsLastNamedArgument for clarity and consistency (#131346)
Change the name of the control variable `SecondArgIsLastNamedArgument`
to `SecondArgIsLastNonVariadicArgument` for clarity and consistency.
Following feedback on earlier PR that was merged:
-
https://github.com/llvm/llvm-project/pull/131238#discussion_r1995690691_
Commit: 17b4be8f63a9a2c17290c8540d84f17a370b1915
https://github.com/llvm/llvm-project/commit/17b4be8f63a9a2c17290c8540d84f17a370b1915
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Move setting name and adding VFs after recipe creation.(NFC)
Recipe creation is the only place where the VF range is restricted. Move
setting the VFs just after initial recipe creation.
Commit: 06546e005d2f9363c51552cfdbe7e69d0bcb5f02
https://github.com/llvm/llvm-project/commit/06546e005d2f9363c51552cfdbe7e69d0bcb5f02
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/unique_object_duplication.h
Log Message:
-----------
[clang][NFC] Fix typo 'initializeation' (#131594)
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: ed57ab0c2b8f359e7937f2c565239bd7cf124a9f
https://github.com/llvm/llvm-project/commit/ed57ab0c2b8f359e7937f2c565239bd7cf124a9f
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
A cmake/Modules/FindLibcCommonUtils.cmake
R llvm/cmake/modules/FindLibcCommonUtils.cmake
Log Message:
-----------
[cmake] Move FindLibcCommonUtils to shared cmake, to fix standalone builds (#131586)
Move `FindLibcCommonUtils` from LLVM's CMake module directory to the
shared top-level CMake directory, as the module is intended to be used
from within the source tree rather than the installed LLVM version. This
fixes standalone offload builds after #131205.
Commit: b79d53caaad7a36b1f20c70ea777fa283d181652
https://github.com/llvm/llvm-project/commit/b79d53caaad7a36b1f20c70ea777fa283d181652
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
A llvm/test/CodeGen/X86/pr131389.ll
Log Message:
-----------
[X86] X86MCInstLower.cpp - printConstant - don't assume the source constant data is smaller than the printed data
Bail out if the constant types aren't compatible
Fixes #131389
Commit: 1e89a76a0490b6c55a3e46ecf967da3e30c9112b
https://github.com/llvm/llvm-project/commit/1e89a76a0490b6c55a3e46ecf967da3e30c9112b
Author: Zhuoran Yin <zhuoryin at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-unsupported.mlir
Log Message:
-----------
[MLIR] Refactor to create vectorization convOp precondition check (#130181)
In corner situations, the vectorization pass may face to lower a conv2d
op and assert in a completely irrelevant location in
vectorizeConvolution() subroutine.
~~This PR rejects the conv2d op early and make the asserted routine to
return failure as a defensive workaround.~~
In addressing this, the PR moved all condition check away from the
`Conv1dGenerator` into the `convOpPreconditionCheck()` function. This
makes the unsupported ops such as conv2d to be rejected early and leave
a cleaner `Conv1dGenerator` constructor.
Commit: 19adc69029ba090d9eae3b89069dee7eadb1bd26
https://github.com/llvm/llvm-project/commit/19adc69029ba090d9eae3b89069dee7eadb1bd26
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/EntryPointStats.cpp
Log Message:
-----------
[analyzer] Add [[maybe_unused]] forgotten in 57e36419b251 (#131617)
Fixes
https://github.com/llvm/llvm-project/pull/131175#discussion_r1998764727
Commit: 1c3a9a853ce68c3c539e7cab21380b9d8b18f426
https://github.com/llvm/llvm-project/commit/1c3a9a853ce68c3c539e7cab21380b9d8b18f426
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
A llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
Log Message:
-----------
[AMDGPU] frame index elimination hit assertion for scavenged nonreg (#130287)
Avoid spilling and fold the offset into `FIOp` when the scavenger fails
to find a free reg during frame index elimination.
Fixes #130120
Commit: 2ff370f45266b14c2a86e6395042a4574701f2d2
https://github.com/llvm/llvm-project/commit/2ff370f45266b14c2a86e6395042a4574701f2d2
Author: Devon Loehr <DKLoehr at users.noreply.github.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/SemaCXX/unnecessary-virtual-specifier.cpp
Log Message:
-----------
Warn about virtual methods in `final` classes (#131188)
There's never any point to adding a `virtual` specifier to methods in a
`final` class, since the class can't be subclassed. This adds a warning
when we notice this happening, as suggested in #131108.
We don't currently implement the second part of the suggestion, to warn
on `virtual` methods which are never overridden anywhere. Although it's
feasible to do this for things with internal linkage (so we can check at
the end of the TU), it's more complicated to implement and it's not
clear it's worth the effort.
I tested the warning by compiling chromium and clang itself. Chromium
resulted in [277 warnings across 109
files](https://github.com/user-attachments/files/19234889/warnings-chromium.txt),
while clang had [38 warnings across 29
files](https://github.com/user-attachments/files/19234888/warnings-clang.txt).
I inspected a subset of the warning sites manually, and they all seemed
legitimate.
This warning is very easy to fix (just remove the `virtual` specifier)
and I haven't seen any false positives, so it's suitable for
on-by-default. However, I've currently made it off-by-default because it
fires at several places in the repo. I plan to submit a followup PR
fixing those places and enabling the warning by default.
Commit: 8bc0f879a05228c58235ded510360da2220f0afd
https://github.com/llvm/llvm-project/commit/8bc0f879a05228c58235ded510360da2220f0afd
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] D16 LDS load/store pseudo instructions in true16 (#131427)
Implement new pseudos with the suffix _t16 which have VGPR_16 as the
store src or load dst. This affects LDS 8 and 16-bit loads and stores.
Lower the pseudos to the existing real Hi/Lo instructions in MC inst
layer with VGPR_32 src or dst
---------
Co-authored-by: Abhinav <abhinav.garg at amd.com>
Commit: b8317df8d8f6dc110edfbf86d8269c912cb2a2a9
https://github.com/llvm/llvm-project/commit/b8317df8d8f6dc110edfbf86d8269c912cb2a2a9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Avoid repeated hash lookups (NFC) (#131553)
Commit: 8789c0083de178fd044e5fb94b3a36c2eec49e0a
https://github.com/llvm/llvm-project/commit/8789c0083de178fd044e5fb94b3a36c2eec49e0a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
Log Message:
-----------
[Transforms] Avoid repeated hash lookups (NFC) (#131554)
Commit: e71686ed1539abe8ec68a4efa010f5ede13e9888
https://github.com/llvm/llvm-project/commit/e71686ed1539abe8ec68a4efa010f5ede13e9888
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
Log Message:
-----------
[TargetParser] Avoid repeated hash lookups (NFC) (#131555)
Commit: 9455df969ef34681d08b2118a2ca2e8b0bd0155b
https://github.com/llvm/llvm-project/commit/9455df969ef34681d08b2118a2ca2e8b0bd0155b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
Log Message:
-----------
[Transforms] Avoid repeated hash lookups (NFC) (#131556)
Commit: 83356f3b62e95b980ca48083aafa4a1b4040d4c9
https://github.com/llvm/llvm-project/commit/83356f3b62e95b980ca48083aafa4a1b4040d4c9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Compile functions lazily (#131596)
Create the Function* handles for all functions we see, but delay the
actual compilation until we really call the function. This speeds up
compile times with the new interpreter a bit.
Commit: 1b237198dc9d308c6d589e01637ec7496b48b3e0
https://github.com/llvm/llvm-project/commit/1b237198dc9d308c6d589e01637ec7496b48b3e0
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M lldb/include/lldb/API/SBProcess.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/StopInfo.h
M lldb/include/lldb/Target/Thread.h
M lldb/include/lldb/Target/ThreadList.h
M lldb/include/lldb/Target/ThreadPlan.h
M lldb/include/lldb/Target/ThreadPlanBase.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/gdbclientutils.py
A lldb/packages/Python/lldbsuite/test/lldbgdbproxy.py
A lldb/packages/Python/lldbsuite/test/lldbreverse.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBThread.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/scripted/ScriptedProcess.h
M lldb/source/Target/Process.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadList.cpp
M lldb/source/Target/ThreadPlanBase.cpp
A lldb/test/API/functionalities/reverse-execution/Makefile
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueBreakpoints.py
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueNotSupported.py
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueWatchpoints.py
A lldb/test/API/functionalities/reverse-execution/main.c
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.cpp
Log Message:
-----------
Reapply "[lldb] Implement basic support for reverse-continue (#125242)" (again) (#128156)
This reverts commit
https://github.com/llvm/llvm-project/commit/87b7f63a117c340a6d9ca47959335fd7ef6c7ad2,
reapplying
https://github.com/llvm/llvm-project/commit/7e66cf74fb4e6a103f923e34700a7b6f20ac2a9b
with a small (and probably temporary)
change to generate more debug info to help with diagnosing buildbot
issues.
Commit: 37c3fbfa5ae9c124fffa4d53df708c688d8584c6
https://github.com/llvm/llvm-project/commit/37c3fbfa5ae9c124fffa4d53df708c688d8584c6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] Add test showing failure to merge concatenatable VPERMV3 nodes
Commit: 269c40fafc80576ab4efcd7fba954fd5588ea118
https://github.com/llvm/llvm-project/commit/269c40fafc80576ab4efcd7fba954fd5588ea118
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
Log Message:
-----------
[X86] Add tests for concatenation of VPERMV nodes
Commit: 52e7ca9279b4cbe30cacca67548347ef5f96b120
https://github.com/llvm/llvm-project/commit/52e7ca9279b4cbe30cacca67548347ef5f96b120
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
Log Message:
-----------
[LLVM][NVPTX] Add support for ldmatrix extensions introduced in PTX 8.6 (#124899)
This commit adds support for the following ldmatrix extensions
introduced in PTX 8.6
- Support for m16n16 with b8 type with mandatory transpose
- Support for m16n16 with m8n16 with source and desitination formats
The above extensions are only supported on sm_100a, sm_101a, sm_120a
Please refer the PTX ISA for more information:
https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-ldmatrix
Commit: 3959bbc1345b9eb99b208e816a86e6a39103c345
https://github.com/llvm/llvm-project/commit/3959bbc1345b9eb99b208e816a86e6a39103c345
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[NFC] Remove trailing white spaces from `llvm/docs/LangRef.rst`
Commit: a4510aa7cb6073ccec63edce3aaed3e6f92563a5
https://github.com/llvm/llvm-project/commit/a4510aa7cb6073ccec63edce3aaed3e6f92563a5
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M flang-rt/cmake/modules/GetToolchainDirs.cmake
Log Message:
-----------
[flang-rt] replace the triple dir to 'aix' for flang-rt to be consistent with clang on AIX. (#130875)
This change is to put `libflang_rt.runtime.a` into
`build/lib/clang/21/lib/aix/libflang_rt.runtime.a`, which is consistent
with clang on AIX.
Commit: 7054655c52e03a2a0d3bca679cb883241679a14e
https://github.com/llvm/llvm-project/commit/7054655c52e03a2a0d3bca679cb883241679a14e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[llvm-exegesis] Add myself as an llvm-exegesis maintainer (#131580)
More people have been interested in exegesis recently, so having a point
of contact would probably be good. Exegesis also never had proper code
owners in the previous system, so adding them now is a decent step
forward.
I'm nominating myself as I'm interested in pushing the project further,
and have a decent amount of experience with the code base. Two of the
original authors, Clement and Guillaume, now have different priorities
at work and are thus not as invested into maintaining exegesis anymore.
Commit: e2c43ba981620cf71ce3ccf004db7c0db4caf8a7
https://github.com/llvm/llvm-project/commit/e2c43ba981620cf71ce3ccf004db7c0db4caf8a7
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
Log Message:
-----------
[NFC][AMDGPU] Auto generate check lines for `llvm/test/CodeGen/AMDGPU/packed-fp32.ll` (#131629)
Commit: eef5ea0c42fc07ef2c948be59b57d0df8ec801ca
https://github.com/llvm/llvm-project/commit/eef5ea0c42fc07ef2c948be59b57d0df8ec801ca
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/X86/pr131359-dead-for-splice.ll
Log Message:
-----------
[VPlan] Account for dead FOR splice simplification in cost model (#131486)
Fixes #131359
After #129645, a first-order recurrence will no longer have it's splice
costed if the VPInstruction::FirstOrderRecurrenceSplice has no users and
is dead.
The legacy cost model didn't account for this, so this accounts for it
in planContainsAdditionalSimplifications to avoid the "VPlan cost model
and legacy cost model disagreed" assertion.
Commit: b00ad366323cee324b0294f6395c33ae4b047e2c
https://github.com/llvm/llvm-project/commit/b00ad366323cee324b0294f6395c33ae4b047e2c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
Log Message:
-----------
[RISCV] Use hasFeature instead of checkFeature in llvm-exegesis. NFC (#131401)
Until recently checkFeature was quite slow. #130936
I was curious where we use checkFeature and noticed these. I thought we
could use hasFeature instead of going through strings.
Commit: 54cb4059da2751758b3ab6dc5630e40b228bcda5
https://github.com/llvm/llvm-project/commit/54cb4059da2751758b3ab6dc5630e40b228bcda5
Author: Vineet Kumar <173554+vntkmr at users.noreply.github.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/combine-fma-negate.ll
Log Message:
-----------
[X86][ISel][FMA] Get a handle on operand nodes when negating FMA (#130176)
When negating an FMA opcode, a new node created for a negated FMA
operand may be deleted while recursively negating another FMA operand.
This causes the following assertion to fail:
```
llc: /root/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7686: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, const llvm::SDLoc&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDNodeFlags): Assertion `N1.getOpcode() != ISD::DELETED_NODE && N2.getOpcode() != ISD::DELETED_NODE && N3.getOpcode() != ISD::DELETED_NODE && "Operand is DELETED_NODE!"' failed.
```
This patch adds a temporary handle on the new negated nodes to prevent
them from being deleted.
For eg. see https://godbolt.org/z/Tq4PvnKM4 .
Co-authored-by: Vineet Kumar <vineetk at hpe.com>
Commit: 67f1c033b8ff07c2713b3cb1209a574129274cbf
https://github.com/llvm/llvm-project/commit/67f1c033b8ff07c2713b3cb1209a574129274cbf
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Remove createReduction. NFCI (#131336)
This is split off from #131300.
A VPReductionRecipe will never have a AnyOf or FindLastIV recurrence, so
when it calls createReduction it always calls createSimpleReduction.
If we replace the call then it leaves createReduction with one user in
VPInstruction::ComputeReductionResult, which we can inline and then
remove.
Commit: 800593a014791e3aa26f04357f580d2dcc87320a
https://github.com/llvm/llvm-project/commit/800593a014791e3aa26f04357f580d2dcc87320a
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Avoid duplicated module flags in the export (#131627)
This commit resolves an issue in the LLVMIR export that caused the
duplication of the "Debug Info Version" module flag, when it was already
in MLIR.
Commit: 561f1d0b7cbbe6f40dca40830ccb4b956bf9ecef
https://github.com/llvm/llvm-project/commit/561f1d0b7cbbe6f40dca40830ccb4b956bf9ecef
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
Log Message:
-----------
[X86] add test coverage for concatenation to 512-bit VPERMILPD nodes
Commit: 9a92fe0f8d34ba0b06b3f831c269d381f3944304
https://github.com/llvm/llvm-project/commit/9a92fe0f8d34ba0b06b3f831c269d381f3944304
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] Add additional test coverage for #109272
Commit: b3c5031b07396959c5d4e7f62d516d63de015358
https://github.com/llvm/llvm-project/commit/b3c5031b07396959c5d4e7f62d516d63de015358
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/cbuffer.hlsl
M clang/test/AST/HLSL/cbuffer_and_namespaces.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/AST/HLSL/resource_binding_attr.hlsl
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M llvm/include/llvm/Frontend/HLSL/HLSLResource.h
Log Message:
-----------
[HLSL] Remove HLSLResource attribute (#130342)
Fixes #104862
Commit: 47f7daab06e4e83f64a1b268da7ada4f50d50349
https://github.com/llvm/llvm-project/commit/47f7daab06e4e83f64a1b268da7ada4f50d50349
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/glob.yaml
Log Message:
-----------
[libc][docs] Add glob implementation status doc and include in CMakeLists (#126923)
These changes tracks `glob.h` for the implementation status of functions
and macros, with respect to the issue ( #122006 ) .
cc @nickdesaulniers
Commit: fbb8929c9d15fdc0001205ee4a7b42a78edc5213
https://github.com/llvm/llvm-project/commit/fbb8929c9d15fdc0001205ee4a7b42a78edc5213
Author: John Harrison <harjohn at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/LLDBUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
R lldb/tools/lldb-dap/Protocol.cpp
R lldb/tools/lldb-dap/Protocol.h
A lldb/tools/lldb-dap/Protocol/ProtocolBase.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolBase.h
A lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
A lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/tools/lldb-dap/Transport.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Updating RequestHandler to encode/decode arguments and response. (#130090)
This is a work in progress refactor to add explicit types instead of
generic 'llvm::json::Value' types to the DAP protocol.
This updates RequestHandler to have take the type of the arguments and
response body for serialization for requests.
The 'source' and 'disconnect' request is updated to show how the new
flow
works and includes serialization handling for optional arguments and
'void'
responses.
This is built on top of #130026
---------
Co-authored-by: Adrian Vogelsgesang <adrian.vogelsgesang at tum.de>
Commit: 681b24132c5d8ce8eafee191a967799dd2a23960
https://github.com/llvm/llvm-project/commit/681b24132c5d8ce8eafee191a967799dd2a23960
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port fbb8929c9d15
Commit: 046041842022f12ab04403e255ceeec25d6ce11c
https://github.com/llvm/llvm-project/commit/046041842022f12ab04403e255ceeec25d6ce11c
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
Log Message:
-----------
[clang][driver][NFC] Remove else after return (#131182)
Commit: c53caae1d0baaf21d63e5f7152171699bcab0750
https://github.com/llvm/llvm-project/commit/c53caae1d0baaf21d63e5f7152171699bcab0750
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libcxx/include/__memory/unique_ptr.h
Log Message:
-----------
[libc++][NFC] Remove dead link in comment
Commit: ca1bde0b91a6129e7bacee0fa67e4331b06dd683
https://github.com/llvm/llvm-project/commit/ca1bde0b91a6129e7bacee0fa67e4331b06dd683
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Check dtor instance pointers for active-ness (#128732)
And diagnose if we're trying to destroy an inactive member of a union.
Commit: cfa07ccdfcf03cbd48086fe9988f97e3a776b02c
https://github.com/llvm/llvm-project/commit/cfa07ccdfcf03cbd48086fe9988f97e3a776b02c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Fix builtin_memchr with non-0 start index (#131633)
Commit: ead9d6a56d764190aa916c5259ab50986f803128
https://github.com/llvm/llvm-project/commit/ead9d6a56d764190aa916c5259ab50986f803128
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/empty-vectorizable-tree.ll
Log Message:
-----------
[SLP]Check VectorizableTree is not empty before accessing elements
Need to check VectorizableTree is not empty before accessing elements.
Fixes #131635
Commit: f6a7306beaf5ba8f62450ab91b7c89a54f6b745f
https://github.com/llvm/llvm-project/commit/f6a7306beaf5ba8f62450ab91b7c89a54f6b745f
Author: darkbuck <michael.hliao at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/CIR/FrontendAction/CMakeLists.txt
M clang/lib/FrontendTool/CMakeLists.txt
Log Message:
-----------
[clang][CIR] Add missing dependency on MLIR headers (#131057)
Commit: 279e82fca7f2fd565c8b8e99bc29e696a910b681
https://github.com/llvm/llvm-project/commit/279e82fca7f2fd565c8b8e99bc29e696a910b681
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
Log Message:
-----------
Revert f9146ccbe940d8b8eb15e7686a511a28eb0abc6b (#131656)
This reverts commit f9146ccbe940d8b8eb15e7686a511a28eb0abc6b
([libc][bazel] explicitly use system-provided errno in Bazel builds.
(#130663))
This change causes problems in Bazel builds where system errno is set to
non-zero before the tests even begin to run - see PR #131650 for the
disucssion on how to address this.
Commit: af5abd9a682d3a7d993f1b4fcae92efe318b835c
https://github.com/llvm/llvm-project/commit/af5abd9a682d3a7d993f1b4fcae92efe318b835c
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
A clang/lib/Headers/hlsl/hlsl_compat_overloads.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
A clang/test/SemaHLSL/BuiltIns/clamp-errors-16bit.hlsl
M clang/test/SemaHLSL/BuiltIns/clamp-errors.hlsl
Log Message:
-----------
[HLSL] add extra scalar vector overloads for clamp (#129939)
Add additional vector scalar overloads for clamp using templates
Add Tests
fixup tests which have changed.
Closes #128230
Commit: 2443fe537f8bf7620c26586034b12a977d14e366
https://github.com/llvm/llvm-project/commit/2443fe537f8bf7620c26586034b12a977d14e366
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port af5abd9a682d
Commit: 911b200ce339ace2d55cd2827bb10ed6a494faae
https://github.com/llvm/llvm-project/commit/911b200ce339ace2d55cd2827bb10ed6a494faae
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/Parse/ParseStmtAsm.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/CodeGenCXX/gnu-asm-constexpr.cpp
M clang/test/Parser/asm.cpp
A clang/test/SemaCXX/gnu-asm-constexpr.cpp
Log Message:
-----------
[Clang] Constant Expressions inside of GCC' asm strings (#131003)
Implements GCC's constexpr string ASM extension
https://gcc.gnu.org/onlinedocs/gcc/Asm-constexprs.html
Commit: 24e88b0e6bc04f16d7353ad9ef07398836adf244
https://github.com/llvm/llvm-project/commit/24e88b0e6bc04f16d7353ad9ef07398836adf244
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libcxx/include/module.modulemap
M libcxx/test/benchmarks/GenerateInput.h
R libcxx/test/benchmarks/algorithms/fill.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/fill.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/fill_n.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/generate.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/generate_n.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/move.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/move_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/remove.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/remove_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/replace.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/reverse.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/reverse_copy.bench.cpp
M libcxx/test/benchmarks/algorithms/modifying/rotate.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/rotate_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/sample.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shift_left.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shift_right.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shuffle.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/swap_ranges.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/transform.binary.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/transform.unary.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/unique.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/unique_copy.bench.cpp
R libcxx/test/benchmarks/algorithms/move.bench.cpp
R libcxx/test/benchmarks/algorithms/move_backward.bench.cpp
R libcxx/test/benchmarks/algorithms/reverse.bench.cpp
Log Message:
-----------
[libc++] Add remaining benchmarks from [alg.modifying.operations] (#127354)
This patch adds benchmarks for all the remaining algorithms in
[alg.modifying.operations] that we didn't already have a benchmark for.
Commit: 20cdffbd2761b2cb33e0968a78de9a427d0ef555
https://github.com/llvm/llvm-project/commit/20cdffbd2761b2cb33e0968a78de9a427d0ef555
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
Log Message:
-----------
[X86] combineConcatVectorOps - extend VPERMILPD handling to support 512-bit types
Commit: bbaf743c461e5e38a72f12f2b6ee6b91674a2a4d
https://github.com/llvm/llvm-project/commit/bbaf743c461e5e38a72f12f2b6ee6b91674a2a4d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] Cleanup test coverage for #109272
We need to add commutated variants (to match the original bug report), some of which are still failing....
Commit: 9eb6b37e397eba7b286777f5502a08876e74d905
https://github.com/llvm/llvm-project/commit/9eb6b37e397eba7b286777f5502a08876e74d905
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
Log Message:
-----------
[RISCV] Put CV_ELW back in XCV DecoderNamespace.
I messed this up in #130800.
Commit: d2e1e3034801da85c495adfffadf1de87f8b4734
https://github.com/llvm/llvm-project/commit/d2e1e3034801da85c495adfffadf1de87f8b4734
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
Log Message:
-----------
[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)
Rename RISCV32GPRPair and RISCV32Only_ to RV32Only. This gives a more
natural home for the P extension RV32 conflicts.
While I was there I made some improvements to the debug messages.
Commit: 6f659b0060d615435ceec53de407a8084656bc98
https://github.com/llvm/llvm-project/commit/6f659b0060d615435ceec53de407a8084656bc98
Author: Jan Voung <jvoung at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.cpp
M clang/include/clang/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.h
M clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
Log Message:
-----------
[clang][dataflow] For bugprone-unchecked-optional-access report range (#131055)
Report the range in diagnostics, in addition to the location
in case the range helps disambiguate a little in chained `->`
expressions.
```
b->a->f->x = 1;
^~~~~~~
```
instead of just:
```
b->a->f->x = 1;
^
```
As a followup we should probably also report the location/range
of an `->` if that operator is used. Like:
```
b->a->f->x = 1;
^~
```
Commit: e3ef5f2928f4077c48aebbddd288442d6ff76b62
https://github.com/llvm/llvm-project/commit/e3ef5f2928f4077c48aebbddd288442d6ff76b62
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/test/SemaHLSL/BuiltIns/fmod-errors.hlsl
Log Message:
-----------
[HLSL] Add bounds checks for the HLSL `fmod` vector arguments and return types (#131035)
Fixes #131024.
- Fixes template for scalar and vector `fmod` intrinsic overloads
- Fixes `fmod` Sema test
Commit: 4ce1d1f1d90d19fb7094f2dcca3b46fef81c1e27
https://github.com/llvm/llvm-project/commit/4ce1d1f1d90d19fb7094f2dcca3b46fef81c1e27
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseSet.h
M llvm/unittests/ADT/DenseSetTest.cpp
Log Message:
-----------
[ADT] Add DenseSet::insert_range (#131567)
This pach adds DenseSet::insert_range, named after
std::map::insert_range from C++23. The intent is to allow a heavy
operation as the argument like:
Set.insert_range(Map[Key]);
Without insert_range, we would have to do:
Set.insert(Map[Key].begin(), Map[Key].end());
or:
auto &M = Map[Key];
Set.insert(M.begin(), M.end());
Neither is elegant.
Commit: 2e6402ca2c6c33ccf41d74383a8e3afb82489410
https://github.com/llvm/llvm-project/commit/2e6402ca2c6c33ccf41d74383a8e3afb82489410
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
Log Message:
-----------
[NFC] Add explicit initializer to PGOCtxProfReader's RootEntryCount
I found that on Clang versions before 11 we suppress the defaulted
constructor because RootEntryCount would not be initialized. This patch
adds an explicit initializer which should suppress this error.
Commit: 6dbe82f061bf494bc91ed458726c8080269f64f6
https://github.com/llvm/llvm-project/commit/6dbe82f061bf494bc91ed458726c8080269f64f6
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/BTF/BTFContext.h
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h
M llvm/include/llvm/DebugInfo/PDB/PDBContext.h
M llvm/lib/DebugInfo/BTF/BTFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/lib/DebugInfo/PDB/PDBContext.cpp
M llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/unittests/DebugInfo/BTF/BTFParserTest.cpp
Log Message:
-----------
[NFC][DebugInfo] Wrap DILineInfo return type with std::optional to handle missing debug info. (#129792)
Currently, `DIContext::getLineInfoForAddress` and
`DIContext::getLineInfoForDataAddress` returns empty DILineInfo when the
debug info is missing for the given address. This is not differentiable
with the case when debug info is found for the given address but the
debug info is default value (filename:linenum is <invalid>:0).
This change wraps the return types of `DIContext::getLineInfoForAddress`
and `DIContext::getLineInfoForDataAddress` with `std::optional`.
Commit: 4336e5edbcc243a246c3cbcefef555f1d63db4cc
https://github.com/llvm/llvm-project/commit/4336e5edbcc243a246c3cbcefef555f1d63db4cc
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP] Sort PHIs by ExtractElements when relevant (#131229)
Considering the PHIs in order of element extracted can lead to better shuffles.
Commit: 0191307bb2583c95d6ee703588c3be1686101061
https://github.com/llvm/llvm-project/commit/0191307bb2583c95d6ee703588c3be1686101061
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Attributes.td
M llvm/test/CodeGen/NVPTX/param-overalign.ll
Log Message:
-----------
[IR] Allow alignstack attribute on return values (#130439)
The PTX target allows an alignment to be specified on both return values
and parameters to allow for more efficient vectorized stores. Currently
we represent these parameter alignments via the "alignstack" attribute,
but must fall back to metadata for the return value. This PR allows
"alignstack" on return values as well.
Commit: 74d4fc0a3ef0082145735eb727eeb67c768b8fb0
https://github.com/llvm/llvm-project/commit/74d4fc0a3ef0082145735eb727eeb67c768b8fb0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Transforms/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/test/Fir/CUDA/cuda-shared-offset.mlir
M flang/test/Fir/CUDA/cuda-shared-to-llvm.mlir
Log Message:
-----------
[flang][cuda][NFC] Use ssa value for offset in shared memory op (#131661)
Switch from attribute to a value as we need to support dynamic offset
when multiple variables are used with dynamic shared memory.
Commit: 128f381650aa7f920495334acfb5f5270d34b978
https://github.com/llvm/llvm-project/commit/128f381650aa7f920495334acfb5f5270d34b978
Author: Viktoria Maximova <viktoria.maksimova at intel.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-composite.ll
Log Message:
-----------
[SPIR-V] Add `OpConstantCompositeContinuedINTEL` instruction (#129086)
Specification:
https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_long_composites.html
Commit: 887cf1f8cea240cd50fb80bc9487b22f67d74263
https://github.com/llvm/llvm-project/commit/887cf1f8cea240cd50fb80bc9487b22f67d74263
Author: Tim Gymnich <tim at gymni.ch>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
A llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Enable vector reductions (#131413)
- Enable llvm vector reductions for AMDGPU.
fixes https://github.com/llvm/llvm-project/issues/114816
Commit: 166937b49dac0919fae362c0deecb723b03be764
https://github.com/llvm/llvm-project/commit/166937b49dac0919fae362c0deecb723b03be764
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
Log Message:
-----------
[LV] Cleanup after expanding SCEV predicate to constant.
In some cases, SCEV isn't able to prove that no wrap checks are needed,
while constant folding in SCEVExpander can. In those cases, we may leave
around IR for computing the trip count, which is unused at this point
but may be re-used later, triggering an assertion when trying to clean
up SCEVExp after vectorization.
Directly run the cleaner after expanding to a constant predicate to
prevent any generated code from being re-used.
Fixes https://github.com/llvm/llvm-project/issues/131281.
Commit: 6d2b8285b3f5f4d8f2ce184aeb14e791400a726d
https://github.com/llvm/llvm-project/commit/6d2b8285b3f5f4d8f2ce184aeb14e791400a726d
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/test/API/functionalities/alias/TestBtAliasRepeat.py
M lldb/test/API/functionalities/data-formatter/data-formatter-objc/TestDataFormatterObjCNSContainer.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/unordered/TestDataFormatterGenericUnordered.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/span/TestDataFormatterLibcxxSpan.py
M lldb/test/API/functionalities/data-formatter/root-reference-children/TestRootReferenceChildren.py
M lldb/test/API/lang/cpp/signed_types/TestSignedTypes.py
M lldb/test/API/lang/objc/foundation/TestObjCMethods.py
M lldb/test/API/source-manager/TestSourceManager.py
Log Message:
-----------
[lldb] Support ordered patterns in lldbtest.expect (#131475)
Change `lldbtest.expect` to require the regexes in `patterns` be found in order – when the
`ordered` parameter is true. This matches the behavior of `substrs`.
The `ordered` parameter is true by default, so this change also fixes tests by either
tweaking the patterns to work in order, or by setting `ordered=False`.
I have often wanted to test with `patterns` and also verify the order. This change
allows that.
Commit: c3f750250a9bec9b37198fb5d344d742e648e32d
https://github.com/llvm/llvm-project/commit/c3f750250a9bec9b37198fb5d344d742e648e32d
Author: Johannes de Fine Licht <johannes.definelicht at nextsilicon.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
Log Message:
-----------
[MLIR][LLVM] Handle floats in Mem2Reg of memset intrinsics (#131621)
This was lacking a bitcast from the shifted integer type into a float.
Other non-struct types than integers and floats will still not be
Mem2Reg'ed.
Also adds special handling for constants to be emitted as a constant
directly rather than relying on followup canonicalization patterns
(`memset` of zero is a case that can appear in the wild).
Commit: 5b9006550d7766f07dd1129e0f369ed28f0a8edb
https://github.com/llvm/llvm-project/commit/5b9006550d7766f07dd1129e0f369ed28f0a8edb
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp
M libcxx/test/std/numerics/c.math/hermite.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.local/local_info.members.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp
Log Message:
-----------
[libc++][NFC] Fix incorrect main() signatures
Commit: ccf21094713e7a080a38f30144ea77b7cacf3064
https://github.com/llvm/llvm-project/commit/ccf21094713e7a080a38f30144ea77b7cacf3064
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
M clang/test/CodeGenOpenCL/kernel-attributes.cl
Log Message:
-----------
[Metadata] Change placeholder from `undef` to `poison` (#131469)
Replace `undef` constant metadata uses with `poison`.
Commit: 1b31646757777c8ef68932ac61084b4bd7af2bc1
https://github.com/llvm/llvm-project/commit/1b31646757777c8ef68932ac61084b4bd7af2bc1
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
Log Message:
-----------
[DFSan] Change placeholders from `undef` to `poison` (#131534)
Use `poison` to create dummy phi nodes instead of `undef`.
Commit: 5f866666a6fb8a1a976a286d2f845809a7108f05
https://github.com/llvm/llvm-project/commit/5f866666a6fb8a1a976a286d2f845809a7108f05
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/unary-expr-or-type-trait.cpp
A clang/test/CIR/CodeGen/unary.cpp
Log Message:
-----------
[CIR] Upstream initial support for unary op (#131369)
This adds support for the cir.unary plus, minus, inc, dec, and not operations for integer, floating point, and boolean types.
Commit: 5bf3f08cc9676ad2ec9b56013f5b3627ce43da7d
https://github.com/llvm/llvm-project/commit/5bf3f08cc9676ad2ec9b56013f5b3627ce43da7d
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
Log Message:
-----------
[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)
This patch updates the latencies as well as occupancies of unit stride,
strided, and indexed load/store instructions in SiFive P400 & P600
scheduling models.
Commit: 584f8cc30554c89fdd27cc9e527416a6e4e2cc45
https://github.com/llvm/llvm-project/commit/584f8cc30554c89fdd27cc9e527416a6e4e2cc45
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-in-stable-dirs.c
A clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang][DependencyScanning] Track modules that resolve from "stable" locations (#130634)
That patch tracks whether all the file & module dependencies of a module
resolve to a stable location. This information will later be queried by
build systems for determining where to store the accompanying pcms.
Commit: 541b8f2e14d495e250a0eefaac4b09ce0e27348f
https://github.com/llvm/llvm-project/commit/541b8f2e14d495e250a0eefaac4b09ce0e27348f
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/Driver/riscv-features.c
Log Message:
-----------
[clang][driver] Use rva22u64_v as the default march for Fuchsia targets (#131183)
Fuchsia supports RVA22 + Vector as outlined in https://fuchsia.dev/fuchsia-src/contribute/governance/rfcs/0234_riscv_abi_rva22+v?hl=en
Commit: c1fabd681fed3e024879f64f2e122e667778b9be
https://github.com/llvm/llvm-project/commit/c1fabd681fed3e024879f64f2e122e667778b9be
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx10.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
Log Message:
-----------
[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)
>From GFX10 onwards it is possible to employ benevolent scheduling of
waves. This patch unconditionally enables, for the `amdhsa` OS, the bit
which controls that capability, as it is beneficial for algorithms that
rely on more complex concurrent coordination and it is generally
performance neutral otherwise.
Commit: ad8f0e27606e337d08501a3085390817d8223c0e
https://github.com/llvm/llvm-project/commit/ad8f0e27606e337d08501a3085390817d8223c0e
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang][DepScan] Pass references to ModuleDeps instead of ModuleID in lookupModuleOutput callbacks, NFCI (#131688)
This allows clients to reference more read-only attributes, like IsInStableDirectories.
Commit: e5ec7bb21b3043022f0e69808b28b863570a6aad
https://github.com/llvm/llvm-project/commit/e5ec7bb21b3043022f0e69808b28b863570a6aad
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/test/Fir/CUDA/cuda-shared-offset.mlir
Log Message:
-----------
[flang][cuda] Set correct offsets for multiple variables in dynamic shared memory (#131674)
Commit: 94426df66a8d7c2321f9e197e5ef9636b0d5ce70
https://github.com/llvm/llvm-project/commit/94426df66a8d7c2321f9e197e5ef9636b0d5ce70
Author: David Tellenbach <dtellenbach at apple.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M compiler-rt/test/profile/instrprof-darwin-exports.c
Log Message:
-----------
[compiler-rt][Darwin][x86] Fix instrprof-darwin-exports test (#131425)
ld64 issues a warning about section alignment which was counted as an
unexpected exported symbol and the test failed.
Fixed by disabling all linker warnings using -Wl,-w.
Commit: 092e25571c09d377d2dde835cf38c5698decadad
https://github.com/llvm/llvm-project/commit/092e25571c09d377d2dde835cf38c5698decadad
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
Log Message:
-----------
AMDGPU: Add REQUIRES: asserts to machine pass violation test
We should promote this to a proper error and not llvm_unreachable
Commit: a2fbc9a8e3d3822cea6f14299285ff0a440d1bf3
https://github.com/llvm/llvm-project/commit/a2fbc9a8e3d3822cea6f14299285ff0a440d1bf3
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILLegalizePass.cpp
A llvm/lib/Target/DirectX/DXILLegalizePass.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll
A llvm/test/CodeGen/DirectX/legalize-i64-extract-insert-elements.ll
A llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalarize-two-calls.ll
Log Message:
-----------
[DirectX] Start the creation of a DXIL Instruction legalizer (#131221)
- Legalize i8 truncation back to original types
- remove sext and truncs
- Legalize i64 indicies for insert\extract elements to i32 indicies
- fixes https://github.com/llvm/llvm-project/issues/126323
- fixes https://github.com/llvm/llvm-project/issues/129757
Commit: cb1d640b037b068b42bcf851cdb4b2b85e378746
https://github.com/llvm/llvm-project/commit/cb1d640b037b068b42bcf851cdb4b2b85e378746
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
Log Message:
-----------
[clang][DepScan] resolve dangling reference to lambda that goes out of
scope.
Fixes buildbots.
Commit: 50f8adb5c018d993a4d8de69970a0b627b7f2258
https://github.com/llvm/llvm-project/commit/50f8adb5c018d993a4d8de69970a0b627b7f2258
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/test/MC/RISCV/rvv/aliases.s
Log Message:
-----------
[RISCV] Accept '0(reg)' in addition to '(reg)' ifor vl1r.v/vl2r.v/vl4r.v/vl8r.v
This matches vl1re8.v, vl2re8.v, vl4re8.v, vl8re8.v.
Commit: d1156fcb56891fb1a426c3e8331a51d47f98a1b8
https://github.com/llvm/llvm-project/commit/d1156fcb56891fb1a426c3e8331a51d47f98a1b8
Author: Alexander Kornienko <alexfh at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__charconv/tables.h
M libcxx/include/__charconv/to_chars_base_10.h
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__charconv/to_chars_result.h
M libcxx/include/__charconv/traits.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/locale
M libcxx/include/module.modulemap
R libcxx/test/benchmarks/locale/num_put.bench.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_pointer.pass.cpp
Log Message:
-----------
Revert "[libc++] Optimize num_put integral functions" (#131613)
Reverts llvm/llvm-project#120859
This change breaks formatting of `0` with `std::showbase` + `std::hex`
or `std::oct`, as well as `+0` with `std::showpos`. I believe the new
behavior is violating the standard. See
https://github.com/llvm/llvm-project/pull/120859#issuecomment-2723970242
and later comments for details and explanation.
Commit: d9c65af62654edfdc1e4ff5589428916e4759302
https://github.com/llvm/llvm-project/commit/d9c65af62654edfdc1e4ff5589428916e4759302
Author: William Moses <gh at wsmoses.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Log Message:
-----------
[MLIR][GPUToNVVM] Support 32-bit isfinite (#131699)
Co-authored-by: Ivan Radanov Ivanov <ivanov.i.aa at m.titech.ac.jp>
Commit: 745e16753fc154ac1601ebaf0ebbcdbfd380b948
https://github.com/llvm/llvm-project/commit/745e16753fc154ac1601ebaf0ebbcdbfd380b948
Author: Nikolay Panchenko <nicholas.panchenko at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/include/llvm/Support/JSON.h
M llvm/lib/Support/JSON.cpp
Log Message:
-----------
[JSON][NFC] Move print method out of NDEBUG || DUMP (#131639)
Commit: 4cb1430c1cc6c6c3ecfb092d3228dd1420332a33
https://github.com/llvm/llvm-project/commit/4cb1430c1cc6c6c3ecfb092d3228dd1420332a33
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
Log Message:
-----------
[mlir][spirv] Fix a crash in `spirv::ISubOp::fold` (#131570)
This PR fixes a crash if `spirv.ISub` is not integer type. Fixes
#131283.
Commit: a5107be0317af73a978431e9448f846974c51fca
https://github.com/llvm/llvm-project/commit/a5107be0317af73a978431e9448f846974c51fca
Author: Tim Gymnich <tim at gymni.ch>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Log Message:
-----------
[NFC][AMDGPU][GlobalISel] Make LLTs constexpr (#131673)
- static const -> constexpr
Commit: 00cad3ed228005fa059c23c55bd35f042b624bf1
https://github.com/llvm/llvm-project/commit/00cad3ed228005fa059c23c55bd35f042b624bf1
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
Log Message:
-----------
[SDAG] Handle extract_subvector in isKnownNeverNaN (#131581)
Propagate nnan across extract_subvector.
Commit: ed19620b8c93f27f322b2f40136e5bd428827e00
https://github.com/llvm/llvm-project/commit/ed19620b8c93f27f322b2f40136e5bd428827e00
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Make VPReductionRecipe a VPRecipeWithIRFlags. NFC (#130881)
This patch change the parent of the VPReductionRecipe from
VPSingleDefRecipe to VPRecipeWithIRFlags and also print/get/drop/control
flags by the VPRecipeWithIRFlags. This will remove the dependency of the
underlying instruction.
This patch also add a new function `setFastMathFlags()` to the
VPRecipeWithIRFlags because the entire reduction chain may contains
multiple instructions. And the underlying instruction may not contains
the corresponding flags for this reduction.
Split from #113903.
Commit: 297f6d9f6b215bd7f58cf500b979b94dedbba7bb
https://github.com/llvm/llvm-project/commit/297f6d9f6b215bd7f58cf500b979b94dedbba7bb
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++] Fix check for _LIBCPP_HAS_NO_WIDE_CHARACTERS in features.py (#131675)
The patch that added the new locale Lit features was created before we
switched to a 0-1 macro for _LIBCPP_HAS_WIDE_CHARACTERS, leading to that
patch referring to the obsolete _LIBCPP_HAS_NO_WIDE_CHARACTERS macro
that is never defined nowadays.
Commit: 3c4b9317916ccd2e18c30b1540589518a4c7c88a
https://github.com/llvm/llvm-project/commit/3c4b9317916ccd2e18c30b1540589518a4c7c88a
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Log Message:
-----------
Rename RISCVMCExpr::VK_RISCV_ to VK_. NFC
They implement relocation operators and are named VK_RISCV_ probably to
avoid confusion with `MCSymbolRefExpr::VariantKind`.
`MCSymbolRefExpr::VariantKind` is discouraged
(https://discourse.llvm.org/t/error-expected-relocatable-expression-with-mctargetexpr/84926/2)
and targets are migrating away from `MCSymbolRefExpr::VariantKind`.
Therefore, there is no need to make the name long in the presence of the
clear `RISCVMCExpr::` prefix.
Pull Request: https://github.com/llvm/llvm-project/pull/131489
Commit: e758237352f70fad028f3947e6f0404e50fec024
https://github.com/llvm/llvm-project/commit/e758237352f70fad028f3947e6f0404e50fec024
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/docs/CommandGuide/llvm-strip.rst
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[docs] Mention --discard-locals/--discard-all change for llvm-strip
PR #130704 updated llvm-strip as well.
Suggested by @nga888
Pull Request: https://github.com/llvm/llvm-project/pull/131491
Commit: c72f7958b04c07afbd0d56b2e4772c741f88de67
https://github.com/llvm/llvm-project/commit/c72f7958b04c07afbd0d56b2e4772c741f88de67
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Fix the build
This is a follow-up for:
commit 3c4b9317916ccd2e18c30b1540589518a4c7c88a
Author: Fangrui Song <i at maskray.me>
Date: Mon Mar 17 20:05:28 2025 -0700
Commit: b9d27ac252265839354fffeacaa8f39377ed7424
https://github.com/llvm/llvm-project/commit/b9d27ac252265839354fffeacaa8f39377ed7424
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/MC/MCExpr.cpp
Log Message:
-----------
[MC] Fix formatting of a comment
Commit: 0813c5cf5f5297a479bdd83df23d59622f8573b0
https://github.com/llvm/llvm-project/commit/0813c5cf5f5297a479bdd83df23d59622f8573b0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/test/MC/RISCV/rvv/aliases.s
Log Message:
-----------
[RISCV] Accept '0(reg)' in addition to '(reg)' for vle1.v/vse1.v
Commit: bdb63208b4130aa3811c6f8b6b8b82c5b069eca9
https://github.com/llvm/llvm-project/commit/bdb63208b4130aa3811c6f8b6b8b82c5b069eca9
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
Log Message:
-----------
[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
This patch replaces use of MachineRegisterInfo's liveIn check with the
machine basicBlock's liveIn. As the MRI's liveIn is inconsistent with
the entry MBB liveIns, when it comes to the machine verifier checks.
PS: Its an alternative solution with respect to #126926.
Commit: 0f34eba48a6b28a20dc09cbb531c1142f7e3549b
https://github.com/llvm/llvm-project/commit/0f34eba48a6b28a20dc09cbb531c1142f7e3549b
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
Log Message:
-----------
[NFC][AArch64] test for fixed-width vector signed division with pow2-divisor and SVE enabled (#130252)
With SVE enabled, this should generate asrd instruction. Subsequent
patch will address this.
Commit: 6be6400848eeec027d0cca0662c105683bcc896b
https://github.com/llvm/llvm-project/commit/6be6400848eeec027d0cca0662c105683bcc896b
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.h
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Log Message:
-----------
[LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (#131562)
TPC is only used to access the option `ShouldEmitDebugEntryValues`.
Commit: 2f808dd0702ba3c364eb4373714a1fb09078909d
https://github.com/llvm/llvm-project/commit/2f808dd0702ba3c364eb4373714a1fb09078909d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Compile most recent function decl (#131730)
We used to always do this because all calls went through the code path
that calls getMostRecentDecl(). Do it now, too.
Commit: 478194116083d4b0be790a7511955447165ed38c
https://github.com/llvm/llvm-project/commit/478194116083d4b0be790a7511955447165ed38c
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/mock-system-header.h
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
Log Message:
-----------
[alpha.webkit.UncountedCallArgsChecker] os_log functions should be treated as safe. (#131500)
…os_log functions should be treated as safe in call arguments checkers.
Also treat __builtin_* functions and __libcpp_verbose_abort functions as
"trivial" for the purpose in call argument checkers.
Commit: 1fbfef9b8ac684483619811d9e90cf8e1f84c6ee
https://github.com/llvm/llvm-project/commit/1fbfef9b8ac684483619811d9e90cf8e1f84c6ee
Author: Petr Hosek <phosek at google.com>
Date: 2025-03-17 (Mon, 17 Mar 2025)
Changed paths:
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
R libc/src/stdio/scanf_core/converter.cpp
M libc/src/stdio/scanf_core/converter.h
M libc/src/stdio/scanf_core/current_pos_converter.h
R libc/src/stdio/scanf_core/float_converter.cpp
M libc/src/stdio/scanf_core/float_converter.h
R libc/src/stdio/scanf_core/int_converter.cpp
M libc/src/stdio/scanf_core/int_converter.h
R libc/src/stdio/scanf_core/ptr_converter.cpp
M libc/src/stdio/scanf_core/ptr_converter.h
M libc/src/stdio/scanf_core/reader.h
R libc/src/stdio/scanf_core/scanf_main.cpp
M libc/src/stdio/scanf_core/scanf_main.h
R libc/src/stdio/scanf_core/string_converter.cpp
M libc/src/stdio/scanf_core/string_converter.h
A libc/src/stdio/scanf_core/string_reader.h
M libc/src/stdio/scanf_core/vfscanf_internal.h
M libc/src/stdio/sscanf.cpp
M libc/src/stdio/vsscanf.cpp
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/scanf_core/converter_test.cpp
M libc/test/src/stdio/scanf_core/reader_test.cpp
Log Message:
-----------
[libc] Templatize the scanf Reader interface (#131037)
This allows specializing the implementation for different targets
without including unnecessary logic and is similar to #111559 which did
the same for printf Writer interface.
Commit: fc38982e93d12e0a77cdd8d9068bafdc79a75ce7
https://github.com/llvm/llvm-project/commit/fc38982e93d12e0a77cdd8d9068bafdc79a75ce7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/SetVector.h
M llvm/unittests/ADT/SetVectorTest.cpp
Log Message:
-----------
[ADT] Add SetVector::insert_range (#131715)
This patch adds SetVector::insert_range for consistency with
DenseSet::insert_range and std::set::insert_range from C++23.
Commit: 2df02548289faa34629814fd851667d45db0bb1b
https://github.com/llvm/llvm-project/commit/2df02548289faa34629814fd851667d45db0bb1b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/SmallSet.h
M llvm/unittests/ADT/SmallSetTest.cpp
Log Message:
-----------
[ADT] Add SmallSet::insert_range (#131717)
This patch adds SmallSet::insert_range for consistency with
DenseSet::insert_range and std::set::insert_range from C++23.
Commit: f6ad65a8248d8fdc03b602891aabbdf715e589b0
https://github.com/llvm/llvm-project/commit/f6ad65a8248d8fdc03b602891aabbdf715e589b0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/unittests/ADT/SmallPtrSetTest.cpp
Log Message:
-----------
[ADT] Add SmallPtrSet::insert_range (#131716)
This pach adds SmallPtrSet::insert_range for consistency with
DenseSet::insert_range and std::set::insert_range from C++23.
Commit: 62204482c02e896d7c86b2483952169968ad1ae5
https://github.com/llvm/llvm-project/commit/62204482c02e896d7c86b2483952169968ad1ae5
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#131722)
Commit: 58dd3eda4e3d0e8a4dd3a5f1267ee259cdb5442c
https://github.com/llvm/llvm-project/commit/58dd3eda4e3d0e8a4dd3a5f1267ee259cdb5442c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[Utils] Avoid repeated hash lookups (NFC) (#131723)
Commit: 57dc71352c75f88e6819314b2b0e81a62bf285e9
https://github.com/llvm/llvm-project/commit/57dc71352c75f88e6819314b2b0e81a62bf285e9
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
Log Message:
-----------
[MLIR][Bufferization] Retire `enforce-aliasing-invariants` (#130929)
Why? This option can lead to incorrect IR if used in isolation, for
example, consider the IR below:
```mlir
func.func @loop_with_aliasing(%arg0: tensor<5xf32>, %arg1: index, %arg2: index) -> tensor<5xf32> {
%c1 = arith.constant 1 : index
%cst = arith.constant 1.000000e+00 : f32
%0 = tensor.empty() : tensor<5xf32>
%1 = linalg.fill ins(%cst : f32) outs(%0 : tensor<5xf32>) -> tensor<5xf32>
// The BufferizableOpInterface says that %2 alias with %arg0 or be a newly
// allocated buffer
%2 = scf.for %arg3 = %arg1 to %arg2 step %c1 iter_args(%arg4 = %arg0) -> (tensor<5xf32>) {
scf.yield %1 : tensor<5xf32>
}
%cst_0 = arith.constant 1.000000e+00 : f32
%inserted = tensor.insert %cst_0 into %1[%c1] : tensor<5xf32>
return %2 : tensor<5xf32>
}
```
If we bufferize with: enforce-aliasing-invariants=false, we get:
```
func.func @loop_with_aliasing(%arg0: memref<5xf32, strided<[?], offset: ?>>, %arg1: index, %arg2: index) -> memref<5xf32, strided<[?], offset: ?>> {
%c1 = arith.constant 1 : index
%cst = arith.constant 1.000000e+00 : f32
%alloc = memref.alloc() {alignment = 64 : i64} : memref<5xf32>
linalg.fill ins(%cst : f32) outs(%alloc : memref<5xf32>)
%0 = scf.for %arg3 = %arg1 to %arg2 step %c1 iter_args(%arg4 = %arg0) -> (memref<5xf32, strided<[?], offset: ?>>) {
%cast = memref.cast %alloc : memref<5xf32> to memref<5xf32, strided<[?], offset: ?>>
scf.yield %cast : memref<5xf32, strided<[?], offset: ?>>
}
%cst_0 = arith.constant 1.000000e+00 : f32
memref.store %cst_0, %alloc[%c1] : memref<5xf32>
return %0 : memref<5xf32, strided<[?], offset: ?>>
}
```
Which is not correct IR since the loop yields the allocation.
I am using this option. What do I need to do now?
If you are using this option in isolation, you are possibly generating
incorrect IR, so you need to revisit your bufferization strategy. If you
are using it together with `copyBeforeWrite,` you simply need to retire
the `enforceAliasingInvariants` option.
Co-authored-by: Matthias Springer <mspringer at nvidia.com>
Commit: 489d1e764e973fc0d46bad93e46ca156ded5b406
https://github.com/llvm/llvm-project/commit/489d1e764e973fc0d46bad93e46ca156ded5b406
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
Log Message:
-----------
[LV][NFC] Pre-commit test for supporting strided accesses. (#130563)
Duplicate riscv-vector-reverse.ll as riscv-vector-reverse-output.ll to
verify all generated IR, not just debug output.
Pre-commit for #128718.
Commit: e614e840bc6419ecde584605f2b813dcda7582e7
https://github.com/llvm/llvm-project/commit/e614e840bc6419ecde584605f2b813dcda7582e7
Author: Matthias Springer <me at m-sp.org>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Transforms/GenerateRuntimeVerification.cpp
M mlir/test/Integration/Dialect/MemRef/cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/MemRef/dim-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/load-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/reinterpret-cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/subview-runtime-verification.mlir
Log Message:
-----------
[mlir][memref] Add runtime verification for `memref.dim` (#130410)
Add runtime verification for `memref.dim`: check that the index is in
bounds.
Also simplify the pass pipeline for all memref runtime verification
checks.
Commit: bd1be8a242384d98ef2087f4571b464e01501f5a
https://github.com/llvm/llvm-project/commit/bd1be8a242384d98ef2087f4571b464e01501f5a
Author: David Green <david.green at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
Log Message:
-----------
[CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (#131526)
>From #106446, this adds a variant of getVectorIdxTy that returns an LLT.
Many uses only look at the width, so a getVectorIdxWidth was added as
the common base.
Commit: 44e4b27aec8639823030dd90eb04afa6545c8352
https://github.com/llvm/llvm-project/commit/44e4b27aec8639823030dd90eb04afa6545c8352
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/test/Driver/apple-arm64-arch.c
M clang/test/Driver/compilation_database_multiarch.c
M clang/test/Driver/darwin-ld-platform-version-macos-requires-darwin.c
M clang/test/Driver/mtargetos-darwin.c
M clang/test/Driver/xros-driver-requires-darwin-host.c
M clang/test/Index/pch-from-libclang.c
Log Message:
-----------
[clang] Fix darwin-related tests' REQUIRES annotation (#130138)
The tests updated by this commit were designed to check features in the
clang's driver and index that require clang to be targgeting a darwin
platform while running on a darwin host. For that, their execution is
currently gated by the `REQUIRES: system-darwin` annotation.
This approach becomes a problem when trying to run such tests on a
cross-compiling build of clang on a darwin platform. When the default
target is not darwin (e.g. via `LLVM_DEFAULT_TARGET_TRIPLE `), the
tests will still run on a darwin host and fail spuriously because of the
mismatch with the target detection.
To fix this issue, this patch introduces an extra condition to the
tests' REQUIRES annotation, `target={{.*}}-{{darwin|macos}}{{.*}}`,
ensuring they only run when the relevant target is present.
Commit: 49b8d8472f9852883677d0a2b192ce1ddd877d0a
https://github.com/llvm/llvm-project/commit/49b8d8472f9852883677d0a2b192ce1ddd877d0a
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-distribute-private.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[OpenMP][MLIR] Support LLVM translation for `distribute` with delayed privatization (#131564)
Adds support for tranlating delayed privatization (`private` and
`firstprivate`) for `omp.distribute` ops.
Commit: c42952a782a65d7988e3cb81e920662cc97c1b1e
https://github.com/llvm/llvm-project/commit/c42952a782a65d7988e3cb81e920662cc97c1b1e
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Add support for match.sync Op (#130718)
This change adds the `match.sync` Op to the MLIR NVVM dialect to
generate the `match.sync` PTX instruction.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-match-sync
Commit: 194eceff4327912e6f9167478262961d50516750
https://github.com/llvm/llvm-project/commit/194eceff4327912e6f9167478262961d50516750
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A clang/test/utils/update_cc_test_checks/Inputs/filter_out_after.c
A clang/test/utils/update_cc_test_checks/Inputs/filter_out_after.c.expected
A clang/test/utils/update_cc_test_checks/filter_out_after.test
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll.expected2
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after2.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after2.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after3.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after3.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/filter_out_after.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
update_test_checks: add new --filter-out-after option (#129739)
Whilst trying to clean up some loop vectoriser IR tests (see
test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
for example) a reviewer on PR #129047 suggested it would be
nice to have an option to stop generating CHECK lines after a
certain point. Typically when performing a transformation with
the loop vectoriser we don't usually care about any CHECK lines
generated for the scalar tail of the loop, since the scalar
loop is kept intact. Previously if you wanted to eliminate such
unwanted CHECK lines you had to run the update script, then
manually delete all the lines corresponding to the scalar loop.
This can be very time consuming if the tests ever need changing.
What I've tried to do here is add a new --filter-out-after
option alongside the existing --filter* options that provides
support for stopping the generation of any CHECK lines beyond
the line that matches the filter. With the existing filter
options we never generate CHECK-NEXT lines, but we still care
about ordering with --filter-out-after so I've amended the
code to ensure we treat this filter differently.
Commit: 036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4
https://github.com/llvm/llvm-project/commit/036c6cb37c5647017f98291b3ecd6fb5a2ee2cf4
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcibi-invalid.s
A llvm/test/MC/RISCV/xqcibi-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779)
This extension adds twelve conditional branch instructions that use an
immediate operand for the source.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs at quicinc.com>
Commit: 1094ffcafbc909cf4caecaf331e97ef16250e42d
https://github.com/llvm/llvm-project/commit/1094ffcafbc909cf4caecaf331e97ef16250e42d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/test/Fir/do_concurrent.fir
M flang/test/Fir/invalid.fir
Log Message:
-----------
[flang][fir] Add MLIR op for `do concurrent` (#130893)
Adds new MLIR ops to model `do concurrent`. In order to make `do
concurrent` representation self-contained, a loop is modeled using 2
ops, one wrapper and one that contains the actual body of the loop. For
example, a 2D `do concurrent` loop is modeled as follows:
```mlir
fir.do_concurrent {
%i = fir.alloca i32
%j = fir.alloca i32
fir.do_concurrent.loop
(%i_iv, %j_iv) = (%i_lb, %j_lb) to (%i_ub, %j_ub) step (%i_st, %j_st) {
%0 = fir.convert %i_iv : (index) -> i32
fir.store %0 to %i : !fir.ref<i32>
%1 = fir.convert %j_iv : (index) -> i32
fir.store %1 to %j : !fir.ref<i32>
}
}
```
The `fir.do_concurrent` wrapper op encapsulates both the actual loop and
the allocations required for the iteration variables. The
`fir.do_concurrent.loop` op is a multi-dimensional op that contains the
loop control and body. See the ops' docs for more info.
Commit: 4ad0aa73b7d1ee36c1b1e06ac585798992075102
https://github.com/llvm/llvm-project/commit/4ad0aa73b7d1ee36c1b1e06ac585798992075102
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/unittests/Transforms/Utils/SSAUpdaterBulkTest.cpp
Log Message:
-----------
[SSAUpdaterBulk] Add expectedly failing loop tests. (#131761)
These tests demonstrate the issue in SSAUpdaterBulk when it calculates
incoming values from loop back edges.
The failures are marked with `EXPECT_NONFATAL_FAILURE`, which is the way
to designate an "expected fail" in the Google Test suite.
Commit: f406b28f8ba0fa660e8a7b6cafc6986675abfcbf
https://github.com/llvm/llvm-project/commit/f406b28f8ba0fa660e8a7b6cafc6986675abfcbf
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
A llvm/test/CodeGen/AArch64/aarch64-sve-ldst-one.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/cttz.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Log Message:
-----------
[AArch64][SVE] Fold integer lane extract and store to FPR store (#129756)
This helps avoid pointless fmovs to GPRs, which may be slow, especially
in streaming mode.
Commit: f7716047c6b1379722e4523d3f3a5177fa50d323
https://github.com/llvm/llvm-project/commit/f7716047c6b1379722e4523d3f3a5177fa50d323
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[Clang][NFC] Cleanup UnaryExprOrTypeTraitExpr itanium mangling code (#131764)
Just removing some code duplication.
Extracted from #131515
Commit: c5fe075eaf92edf31f7b73d38fc59bf56bf4f3bb
https://github.com/llvm/llvm-project/commit/c5fe075eaf92edf31f7b73d38fc59bf56bf4f3bb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
Log Message:
-----------
AMDGPU: Use freeze poison instead of undef in alloca promotion (#131285)
Previously the value created to represent the uninitialized memory
of the alloca was undef. Use freeze poison instead. Enables some
optimization improvements (which need defeating in the limit tests),
but also a few regressions. Seems to leave behind dead code in some
cases too.
Commit: 8392573469b4a111c033ee0887f8115b21e2dcd2
https://github.com/llvm/llvm-project/commit/8392573469b4a111c033ee0887f8115b21e2dcd2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Replace unused export inputs with poison instead of undef (#131286)
Commit: 052eca9ff74eaa6df8e15b6af6161ec2801e61b5
https://github.com/llvm/llvm-project/commit/052eca9ff74eaa6df8e15b6af6161ec2801e61b5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Replace unused update.dpp inputs with poison instead of undef (#131287)
Commit: c180fc80dc1d151e740ae477bfa327aba94704dc
https://github.com/llvm/llvm-project/commit/c180fc80dc1d151e740ae477bfa327aba94704dc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Replace unused permlane inputs with poison instead of undef (#131288)
Commit: 586580742123a8e3c1032369e8a2750c2c49685f
https://github.com/llvm/llvm-project/commit/586580742123a8e3c1032369e8a2750c2c49685f
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/UnixAPIChecker.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
Log Message:
-----------
Reapply "[analyzer] Delay the checker constructions after parsing" (#128369)
Reapply "[analyzer] Delay the checker constructions after parsing"
(#128350)
This reverts commit db836edf47f36ed04cab919a7a2c4414f4d0d7e6, as-is.
Depends on #128368
Commit: 0a21ef9536e0f591d334b230bd388bcb503e27ec
https://github.com/llvm/llvm-project/commit/0a21ef9536e0f591d334b230bd388bcb503e27ec
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
Log Message:
-----------
[AMDGPU] Add SubtargetFeature for dynamic VGPR mode (#130030)
This represents a hardware mode supported only for wave32 compute
shaders. When enabled, we set the `.dynamic_vgpr_en` field of
`.compute_registers` to true in the PAL metadata.
This will be changed to use an attribute after downstream consumers
have been migrated.
Commit: 5d53a88416dbf9e5771ff66ec744f96e59ebabb4
https://github.com/llvm/llvm-project/commit/5d53a88416dbf9e5771ff66ec744f96e59ebabb4
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV] Change RISCVMCExpr::VK_RISCV_None to RISCVMCExpr::VK_None (#131774)
Fix RISCVMCExpr::VK_RISCV_None which were added in #130779
Commit: 31e98c70370c7498891d4fb075a6b2b81885b0dd
https://github.com/llvm/llvm-project/commit/31e98c70370c7498891d4fb075a6b2b81885b0dd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/abs-codesize.ll
R llvm/test/Analysis/CostModel/X86/abs-latency.ll
R llvm/test/Analysis/CostModel/X86/abs-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/abs.ll
Log Message:
-----------
[CostModel][X86] merge abs costs tests using -cost-kind=all (#131619)
Now that we have #130490 - merge the cost test files to avoid bitrot
Lots more set of files to do - but this is give an example
Commit: 9cf46fb2303627fd2c74ed88dcd9f3f8cbfe0c93
https://github.com/llvm/llvm-project/commit/9cf46fb2303627fd2c74ed88dcd9f3f8cbfe0c93
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Lex/Lexer.h
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/LiteralSupport.cpp
A clang/test/C/C2y/n3353.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add octal prefixes, deprecate unprefixed octals (#131626)
WG14 N3353 added support for 0o and 0O as octal literal prefixes. It
also deprecates use of octal literals without a prefix, except for the
literal 0.
This feature is being exposed as an extension in older C language modes
as well as in all C++ language modes.
Commit: 332f0603635d06986d6d3c8c9ba4fee04c7cab18
https://github.com/llvm/llvm-project/commit/332f0603635d06986d6d3c8c9ba4fee04c7cab18
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
A llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
A llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
Log Message:
-----------
[SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (#130616)
The language reference says about inbounds geps that "if the
getelementptr has any non-zero indices[...] [t]he base pointer has an in
bounds address of the allocated object that it is based on [and]
[d]uring the successive addition of offsets to the address, the
resulting pointer must remain in bounds of the allocated object at each
step."
If (gep inbounds p, (a + 5)) is translated to (gep [inbounds] (gep p,
a), 5) with p pointing to the beginning of an object and a=-4, as the
example in the comments suggests, that's the case for neither of the
resulting geps. Therefore, we need to clear the inbounds flag for both
geps.
We might want to use ValueTracking to check if a is known to be
non-negative to preserve the inbounds flags.
For the AMDGPU tests with scratch instructions, removing the unsound
inbounds flag means that AMDGPUDAGToDAGISel::isFlatScratchBaseLegal sees
no NUW flag at the pointer add, which prevents generation of scratch
instructions with immediate offsets.
For SWDEV-516125.
Commit: aea3ad8bd3a35adc021cf80b97fad073ece8737b
https://github.com/llvm/llvm-project/commit/aea3ad8bd3a35adc021cf80b97fad073ece8737b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] canCreateUndefOrPoisonForTargetNode - add handling for VPERMV3 intrinsic opcodes (#131768)
We already handle the X86ISD::VPERMV3 node type, but if we can handle equivalent cases before intrinsic lowering we can simplify the code further - e.g. #109272 before constant BUILD_VECTOR nodes gets lowered to constant pool loads.
Commit: 2586e7fcd8ea8485867a2af11daf8a4f42ece704
https://github.com/llvm/llvm-project/commit/2586e7fcd8ea8485867a2af11daf8a4f42ece704
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
Log Message:
-----------
[LV][NFC] Tidy up partial reduction tests with filter-out-after option (#129047)
A few test files seemed to have been edited after using the
update_test_checks.py script, which can make life hard for
developers when trying to update these tests in future
patches. Also, the tests still had this comment at the top
; NOTE: Assertions have been autogenerated by ...
which could potentially be confusing, since they've not
strictly been auto-generated.
I've attempted to keep the spirit of the original tests by
excluding all CHECK lines after the scalar.ph IR block,
however I've done this by using a new option called
--filter-out-after to the update_test_checks.py script.
Commit: 3d631914677b58a5479b310f480ac76e27d41e7e
https://github.com/llvm/llvm-project/commit/3d631914677b58a5479b310f480ac76e27d41e7e
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-trunc-nowrap.ll
Log Message:
-----------
[X86] Ignore NSW when DstSVT is i32 (#131755)
We don't have PACKSS for i64->i32.
Fixes: https://godbolt.org/z/qb8nxnPbK, which was introduced by ddd2f57b
Commit: 23743f5bf974ed1171fd8123f8d2af0f43be3596
https://github.com/llvm/llvm-project/commit/23743f5bf974ed1171fd8123f8d2af0f43be3596
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/Support/ELFAttrParserExtended.h
A llvm/test/MC/AArch64/build-attributes-asm-arch-specific-empty.s
A llvm/test/MC/AArch64/build-attributes-asm-arch-specific.s
Log Message:
-----------
[readobj][ELFExtendedAttrParser] Add destructor with error handling (#131783)
ELFExtendedAttrParser lacked a destructor that properly handled errors,
causing `llvm-readobj --arch-specific` to crash when the AArch64 Build
Attributes section was empty.
This commit adds error handling in the destructor and introduces test
files for `--arch-specific` to cover both an empty AArch64 Build
Attributes section and a populated one.
Fixes:
https://github.com/sivan-shani/llvm-project/commit/b1ebfac1859c4fd1db3620098f6af4fd98e6174d
Commit: 428b320bf31329559ee9f8dd888be4f86cfa68e8
https://github.com/llvm/llvm-project/commit/428b320bf31329559ee9f8dd888be4f86cfa68e8
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
Log Message:
-----------
[libc++] Fix allocate_at_least test that assumes the size_type of the allocator (#131682)
If the size_type of the allocator is not the same as std::size_t, this
test would fail.
Commit: 84e44ae6b7319b7f02156d8ca12548f225299e91
https://github.com/llvm/llvm-project/commit/84e44ae6b7319b7f02156d8ca12548f225299e91
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCInstrAnalysis.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump] Pass MCSubtargetInfo to findPltEntries (NFC) (#131773)
It allows access to subtarget features, collected in llvm-objdump.cpp,
from findPltEntries, which will be used in
https://github.com/llvm/llvm-project/pull/130764.
Commit: 83658ddb1b58fa10cf5f8ac8dfbe794b7a3701bc
https://github.com/llvm/llvm-project/commit/83658ddb1b58fa10cf5f8ac8dfbe794b7a3701bc
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/distribute.f90
M flang/test/Lower/OpenMP/order-clause.f90
M flang/test/Transforms/stack-arrays-hlfir.f90
Log Message:
-----------
[flang][OpenMP] Enable delayed privatization by default for `omp.distribute` (#131574)
Switches delayed privatization for `omp.distribute` to be on by default:
controlled by the `-openmp-enable-delayed-privatization` instead of by
`-openmp-enable-delayed-privatization-staging`.
### GFortran & Fujitsu test suite results:
#### gfotran test-suite (this PR):
```
Testing Time: 34.51s
Passed: 6569
```
#### Fujitsu without changes (commit: 0813c5cf5f52):
```
Testing Time: 155.39s
Passed : 88325
Failed : 156
Executable Missing: 408
```
#### Fujitsu with changes (this PR):
```
Testing Time: 158.54s
Passed : 88325
Failed : 156
Executable Missing: 408
```
Commit: cbc5c11feca0a65a7731de8d6eb14fddf2f233aa
https://github.com/llvm/llvm-project/commit/cbc5c11feca0a65a7731de8d6eb14fddf2f233aa
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/declare-mapper.f90
Log Message:
-----------
[MLIR][OpenMP] Add Lowering support for implicitly linking to default declare mappers (#131006)
Commit: 4f5eed0a37cfeac9de0964ce1a9ecb72b804f1ed
https://github.com/llvm/llvm-project/commit/4f5eed0a37cfeac9de0964ce1a9ecb72b804f1ed
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/bswap-codesize.ll
R llvm/test/Analysis/CostModel/X86/bswap-latency.ll
R llvm/test/Analysis/CostModel/X86/bswap-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bswap.ll
Log Message:
-----------
[CostModel][X86] merge bswap costs tests using -cost-kind=all (#131784)
Commit: a2d7451a13ad25a9c6bb96d0910ee700d863e030
https://github.com/llvm/llvm-project/commit/a2d7451a13ad25a9c6bb96d0910ee700d863e030
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/bitreverse-codesize.ll
R llvm/test/Analysis/CostModel/X86/bitreverse-latency.ll
R llvm/test/Analysis/CostModel/X86/bitreverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse.ll
Log Message:
-----------
[CostModel][X86] merge bitreverse costs tests using -cost-kind=all (#131791)
Commit: 22c6674f1d9cfbbf485f2da4f8dfbd80d666d02f
https://github.com/llvm/llvm-project/commit/22c6674f1d9cfbbf485f2da4f8dfbd80d666d02f
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
A llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Add Dense Math binary integer outer-Product accumulate to DMR Instructions (#130791)
This commit adds the following Dense Math Facility integer calculation
instructions: dmxvi8gerx4, dmxvi8gerx4pp, dmxvi8gerx4spp, pmdmxvi8gerx4,
pmdmxvi8gerx4pp, and pmdmxvi8gerx4spp, along with their corresponding
intrinsics and tests.
Commit: 2fbfbf499eabb84024541060c61f0d88e882c167
https://github.com/llvm/llvm-project/commit/2fbfbf499eabb84024541060c61f0d88e882c167
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M cmake/Modules/FindPrefixFromConfig.cmake
Log Message:
-----------
[cmake] Resolve symlink when finding install prefix (#124743)
When determining the install prefix in LLVMConfig.cmake etc resolve
symlinks in CMAKE_CURRENT_LIST_FILE first. The motivation for this is to
support symlinks like `/usr/lib64/cmake/llvm` to
`/usr/lib64/llvm19/lib/cmake/llvm`. This only works correctly if the
paths are relative to the resolved symlink.
It's worth noting that this *mostly* already works out of the box,
because cmake automatically does the symlink resolution when the library
is found via CMAKE_PREFIX_PATH. It just doesn't happen when it's found
via the default prefix path.
Commit: 1bb8b656a9dcdae3863508b8f33bd713e953636d
https://github.com/llvm/llvm-project/commit/1bb8b656a9dcdae3863508b8f33bd713e953636d
Author: OverMighty <its.overmighty at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/test/src/math/AddTest.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/SubTest.h
A libc/test/src/math/add_same_type_test.cpp
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/SubTest.h
A libc/test/src/math/smoke/add_same_type_test.cpp
A libc/test/src/math/smoke/sub_same_type_test.cpp
A libc/test/src/math/sub_same_type_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
Log Message:
-----------
[libc][math] Fix incorrect logic in fputil::generic::add_or_sub (#116129)
Fixes incorrect logic that went unnoticed until the function was tested
with output and input types that have the same underlying floating-point
format.
Commit: 8f66fb784291c897a965a9ee4c280e314dc8cee4
https://github.com/llvm/llvm-project/commit/8f66fb784291c897a965a9ee4c280e314dc8cee4
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalMerge.h
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
A llvm/test/Transforms/GlobalMerge/constants.ll
Log Message:
-----------
[GlobalMerge] Fix handling of const options
For the NewPM, the merge-const option was assigned to an unused
option field. Assign it to the correct one. The merge-const-aggressive
option was not supported -- and invalid options were silently ignored.
Accept it and error on invalid options.
For the LegacyPM, the corresponding cl::opt options were ignored when
called via opt rather than llc.
Commit: ca87823438e312f4fc7f13bda6ced448e4216cf6
https://github.com/llvm/llvm-project/commit/ca87823438e312f4fc7f13bda6ced448e4216cf6
Author: Vy Nguyen <vyng at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/unittests/Core/TelemetryTest.cpp
Log Message:
-----------
[LLDB][NFC]Refactor common test setup into SetUp method (#131203)
Commit: d85a81b4e4cfc0fdc7c259d64f847e7bbeee56d2
https://github.com/llvm/llvm-project/commit/d85a81b4e4cfc0fdc7c259d64f847e7bbeee56d2
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/docs/ClangOffloadBundler.rst
M clang/include/clang/Driver/OffloadBundler.h
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPUtility.cpp
M clang/test/Driver/clang-offload-bundler-asserts-on.c
M clang/test/Driver/clang-offload-bundler-standardize.c
M clang/test/Driver/clang-offload-bundler.c
M clang/test/Driver/hip-link-bc-to-bc.hip
M clang/test/Driver/hip-link-bundle-archive.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
M llvm/utils/lit/lit/llvm/config.py
Log Message:
-----------
[OffloadBundler] Rework the ctor of `OffloadTargetInfo` to support AMDGPU's generic target (#122629)
The current parsing logic for the target string assumes it follows the
format `<kind>-<triple>-<target id>:<feature>`, such as
`hipv4-amdgcn-amd-amdhsa-gfx1030:+xnack`.
Specifically, it assumes that `<target id>` does not contain any `-`,
relying on `rsplit` for parsing.
However, this assumption breaks for AMDGPU's generic targets, which may
contain one or more `-`, such as `gfx10-3-generic` or `gfx12-generic`.
As a result, the existing approach using `rstrip` is no longer reliable.
This patch reworks the parsing logic to handle target strings more
robustly, including support for generic targets.
The bundler now strictly requires a 4-field target triple.
Additionally, a new Python helper function has been added to `config.py`
to normalize the target triple into the 4-field format when it is not,
ensuring tests pass reliably.
Commit: aab4ce4d5e480c440f3ec2506068164fafa9aa55
https://github.com/llvm/llvm-project/commit/aab4ce4d5e480c440f3ec2506068164fafa9aa55
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
Log Message:
-----------
[NFC][shrinkwrap] Add test point to capture the prologue and epilogue insertion by shrinkwrap pass for powerpc. (#131192)
This is NFC patch to capture the insertion of prologue and epilogue by
`shrinkwrap` pass for Powerpc target for functions that contain llvm
`__builtin_frame_address`.
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Commit: 034dd4c26f736a36aa87de69b8fd7b5460d3752a
https://github.com/llvm/llvm-project/commit/034dd4c26f736a36aa87de69b8fd7b5460d3752a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/ctlz-codesize.ll
R llvm/test/Analysis/CostModel/X86/ctlz-latency.ll
R llvm/test/Analysis/CostModel/X86/ctlz-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/ctlz.ll
Log Message:
-----------
[CostModel][X86] merge ctlz costs tests using -cost-kind=all (#131797)
Commit: 3ea89e0611b103e73c9d11028ebf24ffae61e248
https://github.com/llvm/llvm-project/commit/3ea89e0611b103e73c9d11028ebf24ffae61e248
Author: Joel Wee <joelwee at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Fix Bazel after 1fbfef9
Commit: f6b1b91a3d1ac403c6f53c70e9871bd22f805a9f
https://github.com/llvm/llvm-project/commit/f6b1b91a3d1ac403c6f53c70e9871bd22f805a9f
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
Log Message:
-----------
[LV][NFC] Regenerate CHECK lines in some tests (#131799)
Regenerates CHECK lines in tests that are affected by
PR #130565 to aid reviews.
Commit: f179daf77b180467edd1e0eb208b5b8988b28850
https://github.com/llvm/llvm-project/commit/f179daf77b180467edd1e0eb208b5b8988b28850
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp:121:3:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Commit: 075324461d4179f85d2b94397b11b9dfb788e0f5
https://github.com/llvm/llvm-project/commit/075324461d4179f85d2b94397b11b9dfb788e0f5
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/unittests/ADT/SmallPtrSetTest.cpp
Log Message:
-----------
[ADT] Use separate variables in a unit test for SmallPtrSet (NFC) (#131748)
Commit: 2c56383de5ef665b7380225e777e716ee7a9b1be
https://github.com/llvm/llvm-project/commit/2c56383de5ef665b7380225e777e716ee7a9b1be
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
Log Message:
-----------
[Hexagon] Avoid repeated hash lookups (NFC) (#131719)
Commit: 695a007310c7552f74488c5b498470708661e705
https://github.com/llvm/llvm-project/commit/695a007310c7552f74488c5b498470708661e705
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86PadShortFunction.cpp
Log Message:
-----------
[X86] Avoid repeated hash lookups (NFC) (#131725)
Commit: 127eb39a8ca9625c2ff078bcb05d2a53ee995423
https://github.com/llvm/llvm-project/commit/127eb39a8ca9625c2ff078bcb05d2a53ee995423
Author: Aleksandr Korepanov <alexander.korepanov at jetbrains.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/PDB/PDBTypes.h
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/PDBVariantTest.cpp
Log Message:
-----------
[LLVM][PDB] Use IsUnsigned flag for APInt correctly (#131598)
This patch fixes an assertion that occurs in `APInt`.
The assertion can be reproduced with LLDB test
`python_api/thread/TestThreadAPI.py` (it fails).
Commit: 02b4522358f29dbe13f628647f99b28a0307a56b
https://github.com/llvm/llvm-project/commit/02b4522358f29dbe13f628647f99b28a0307a56b
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/descriptor.h
Log Message:
-----------
[NFC][flang] Added deduction guide for StaticDescriptor class. (#131690)
I keep getting these warnings when building with clang-17:
`warning: 'StaticDescriptor' may not intend to support class template
argument deduction [-Wctad-maybe-unsupported]`
This change should help avoiding them.
Commit: e0bcf3aa0b641a9f72160491f68a34b7be14adc7
https://github.com/llvm/llvm-project/commit/e0bcf3aa0b641a9f72160491f68a34b7be14adc7
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/fir-ops.fir
Log Message:
-----------
[flang] Allow no type parameters for fir.pack_array. (#131662)
Arrays with assumed-length types are represented with a box
without explicit length parameters. This patch fixes the verification
to allow it for `fir.pack_array`.
Commit: 351bcd9fe229121fac58e051f9a83dce2d3066ae
https://github.com/llvm/llvm-project/commit/351bcd9fe229121fac58e051f9a83dce2d3066ae
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/include/__vector/vector_bool.h
Log Message:
-----------
[libc++][NFC] Add a comment that an include is a workaround
Commit: 64cf6f9721c48667c65aab91b94d1ba4c2452978
https://github.com/llvm/llvm-project/commit/64cf6f9721c48667c65aab91b94d1ba4c2452978
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
Log Message:
-----------
[gn build] Port 127eb39a8ca9
Commit: ea107d5c63e09347b01b250a6211974d7ed57efe
https://github.com/llvm/llvm-project/commit/ea107d5c63e09347b01b250a6211974d7ed57efe
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Analysis/ProgramPoint.h
M clang/include/clang/StaticAnalyzer/Core/Checker.h
M clang/include/clang/StaticAnalyzer/Core/CheckerManager.h
M clang/lib/StaticAnalyzer/Core/AnalyzerOptions.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp
Log Message:
-----------
[NFC][analyzer] Use `CheckerBase::getName` in checker option handling (#131612)
The virtual method `ProgramPointTag::getTagDescription` had two very
distinct use cases:
- It is printed in the DOT graph visualization of the exploded graph
(that is, a debug printout).
- The checker option handling code used it to query the name of a
checker, which relied on the coincidence that in `CheckerBase` this
method is defined to be equivalent with `getName()`.
This commit switches to using `getName` in the second use case, because
this way we will be able to properly support checkers that have multiple
(separately named) parts.
The method `reportInvalidCheckerOptionName` is extended with an
additional overload that allows specifying the `CheckerPartIdx`. The
methods `getChecker*Option` could be extended analogously in the future,
but they are just convenience wrappers around the variants that directly
take `StringRef CheckerName`, so I'll only do this extension if it's
needed.
Commit: c33ef4f2d42bce2f41bff9844dfaa785a3a74b68
https://github.com/llvm/llvm-project/commit/c33ef4f2d42bce2f41bff9844dfaa785a3a74b68
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
Log Message:
-----------
[RISCV] Reorder RISCVInstrInfoXCV.td to separate Operands, SDNodeXForms, formats, and instructions into separate sections. NFC (#131411)
This is more consistent with some of our other InstrInfo.td file.
Commit: 05dbabe329441541ae4896c8bf5c85f8446ba4ba
https://github.com/llvm/llvm-project/commit/05dbabe329441541ae4896c8bf5c85f8446ba4ba
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/ctpop-codesize.ll
R llvm/test/Analysis/CostModel/X86/ctpop-latency.ll
R llvm/test/Analysis/CostModel/X86/ctpop-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/ctpop.ll
Log Message:
-----------
[CostModel][X86] merge ctpop costs tests using -cost-kind=all (#131802)
Commit: 6ada38b248ef80a224fd2f48841b22ae3bbf5a7b
https://github.com/llvm/llvm-project/commit/6ada38b248ef80a224fd2f48841b22ae3bbf5a7b
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
Log Message:
-----------
[RISCV][test] Add tests for sinking NOT to be fold into ANDN/ORN/XNOR/VANDN
Commit: 2175c6cb38e7bb7701219a5081f22e7877ab0380
https://github.com/llvm/llvm-project/commit/2175c6cb38e7bb7701219a5081f22e7877ab0380
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
M llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
Log Message:
-----------
[RISCV] Set AllocationPriority in line with LMUL (#131176)
This mechanism causes the greedy register allocator to prefer allocating
register classes with higher priority first. This helps to ensure that
high LMUL registers obtain a register without having to go through the
eviction mechanism. In practice, it seems to cause a bunch of code
churn, and some minor improvement around widening and narrowing
operations.
In a few of the widening tests, we have what look like code size
regressions because we end up with two smaller register class copies
instead of one larger one after the instruction. However, in any larger
code sequence, these are likely to be folded into the producing
instructions. (But so were the wider copies after the operation.)
Two observations:
1) We're not setting the greedy-regclass-priority-trumps-globalness flag
on the register class, so this doesn't help long mask ranges. I
thought about doing that, but the benefit is non-obvious, so I
decided it was worth a separate change at minimum.
2) We could arguably set the priority higher for the register classes
that exclude v0. I tried that, and it caused a whole bunch of
further churn. I may return to it in a separate patch.
Commit: df544b73e4206b4fd683d2c37012b4f78e8084ac
https://github.com/llvm/llvm-project/commit/df544b73e4206b4fd683d2c37012b4f78e8084ac
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
Log Message:
-----------
[CostModel][X86] merge vector shifts costs tests using -cost-kind=all (#131806)
Commit: e8f79eb8980094d62a85c4a6da95e0de36c505a8
https://github.com/llvm/llvm-project/commit/e8f79eb8980094d62a85c4a6da95e0de36c505a8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/cttz-codesize.ll
R llvm/test/Analysis/CostModel/X86/cttz-latency.ll
R llvm/test/Analysis/CostModel/X86/cttz-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/cttz.ll
Log Message:
-----------
[CostModel][X86] merge cttz costs tests using -cost-kind=all (#131810)
Commit: e4d910e80dc294ac3416ee0e2dfbef914d559b90
https://github.com/llvm/llvm-project/commit/e4d910e80dc294ac3416ee0e2dfbef914d559b90
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/cxx2c-enum-compare.cpp
Log Message:
-----------
[Clang] Demote mixed enumeration arithmetic error to a warning (#131811)
In C++, defaulted to an error.
C++ removed these features but the removal negatively impacts users.
Fixes #92340
Commit: 4f7dc99a8a3e34e925ef66e7069b01b811e837ba
https://github.com/llvm/llvm-project/commit/4f7dc99a8a3e34e925ef66e7069b01b811e837ba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
Log Message:
-----------
[RISCV] Use MnemonicAlias instead of InstAlias for some vector instructions. NFC (#131732)
To make this work we have to apply mnemonic aliases before looking up
custom operand parsing.
Commit: 467e5a1d41d63fd1c80fee14a8d99d32515c26d6
https://github.com/llvm/llvm-project/commit/467e5a1d41d63fd1c80fee14a8d99d32515c26d6
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcisim-invalid.s
A llvm/test/MC/RISCV/xqcisim-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)
This extension adds 10 instructions that provide hints to the interface
simulation environment.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/
This patch adds assembler only support.
Commit: b391e80f52f4248e4e2b766c25f83d5e62ef2d56
https://github.com/llvm/llvm-project/commit/b391e80f52f4248e4e2b766c25f83d5e62ef2d56
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/include/bitset
Log Message:
-----------
[libc++] Remove redundant assignments in bitset string-like constructors (#121424)
The following three string-like constructors for `std::bitset`
- `bitset(const CharT* str, std::size_t n, CharT zero, CharT one)`;
- `bitset(const std::basic_string<CharT, Traits, Alloc>& str, typename
std::basic_string<CharT, Traits, Alloc>::size_type pos, CharT zero,
CharT one)`;
- `bitset(std::basic_string_view<CharT, Traits> str, std::size_t pos,
std::size_t n, CharT zero, CharT one)`
already initialize the underlying storage array to all zeroes via
default-constructor of the base class `__bitset`. Therefore,
re-assigning the storage array to zeroes via `std::fill_n` in the
string-like constructors is truly redundant.
Commit: a4dc02c0e75f1880c2ce1641212830c2b8616aad
https://github.com/llvm/llvm-project/commit/a4dc02c0e75f1880c2ce1641212830c2b8616aad
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Rename VPReverseVectorPointerRecipe to VPVectorEndPointerRecipe. NFC (#131086)
After #128718 lands there will be two ways of performing a reversed
widened memory access, either by performing a consecutive unit-stride
access and a reverse, or a strided access with a negative stride.
Even though both produce a reversed vector, only the former needs
VPReverseVectorPointerRecipe which computes a pointer to the last
element of each part. A strided reverse still needs a pointer to the
first element of each part so it will use VPVectorPointerRecipe.
This renames VPReverseVectorPointerRecipe to VPVectorEndPointerRecipe to
clarify that a reversed access may not necessarily need a pointer to the
last element.
Commit: 3d083777efd1649d156a8e6da77022f801cc70f5
https://github.com/llvm/llvm-project/commit/3d083777efd1649d156a8e6da77022f801cc70f5
Author: OverMighty <its.overmighty at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/utils/MPFRWrapper/MPFRUtils.cpp
Log Message:
-----------
[libc] Fix compile error in MPFRWrapper when float128 is long double (#131821)
See https://lab.llvm.org/buildbot/#/builders/104/builds/18422.
Commit: 70357a21373c73fa137c7dff9c6030af75301b21
https://github.com/llvm/llvm-project/commit/70357a21373c73fa137c7dff9c6030af75301b21
Author: Christian von Elm <christian.von_elm at tu-dresden.de>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
Log Message:
-----------
[OpenMP] [OMPD] gdb plugin: remove 'imp' import (#112331)
The 'imp' library was removed in Python 3.12.
As the code never uses the imp library, the import is simply removed.
Commit: 33e5d013b7f7a6ae136a058f842b30c87623ecfb
https://github.com/llvm/llvm-project/commit/33e5d013b7f7a6ae136a058f842b30c87623ecfb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-load.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i32.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i64.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i8.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-reverse.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-single-src.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
Log Message:
-----------
[CostModel][X86] merge vector shuffle costs tests using -cost-kind=all (#131819)
Commit: 6542cf1973208a83b2f883f2143464c4fdbac9eb
https://github.com/llvm/llvm-project/commit/6542cf1973208a83b2f883f2143464c4fdbac9eb
Author: Igor Kudrin <ikudrin at accesssoftek.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
M lldb/unittests/Platform/CMakeLists.txt
A lldb/unittests/Platform/gdb-server/CMakeLists.txt
A lldb/unittests/Platform/gdb-server/PlatformRemoteGDBServerTest.cpp
Log Message:
-----------
[lldb/platform-gdb] Do not assume a persistent connection (#131736)
After https://reviews.llvm.org/D116539, when `m_gdb_client_up` in
`PlatformRemoteGDBServer` is not null, the connection to a server is
expected to exist. However,
`PlatformRemoteGDBServer::DisconnectRemote()` is not the only way to
close the connection;
`GDBRemoteCommunication::WaitForPacketNoLock()` can disconnect if the
server stops responding, and in this case `m_gdb_client_up` is not
cleared. The patch removes this assumption and checks the connection
status directly.
Commit: dea5aa73fa1984eddde14308803bdfca56f2bc14
https://github.com/llvm/llvm-project/commit/dea5aa73fa1984eddde14308803bdfca56f2bc14
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
AMDGPU: Move insertion into V2SCopies map (#130776)
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr->vgpr phi inputs multiple times
which
would trigger a use after free.
I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for
every
input operand, but I will address that separately.
Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.
Commit: 27d8bd3dcab9819e1d28270be634f62bbec925cb
https://github.com/llvm/llvm-project/commit/27d8bd3dcab9819e1d28270be634f62bbec925cb
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
A clang/test/CIR/CodeGen/cast.cpp
A clang/test/CIR/IR/cast.cir
A clang/test/CIR/Lowering/cast.cir
Log Message:
-----------
[CIR] Upstream CastOp and scalar conversions (#130690)
This patch upstreams ClangIR's CastOp with the following exceptions:
- No Fixed/FP conversions
- No casts between value categories
- No complex casts
- No array_to_ptrdecay
- No address_space
- No casts involving record types (member pointers, base/derived casts)
- No casts specific to ObjC or OpenCL
---------
Co-authored-by: Morris Hafner <mhafner at nvidia.com>
Co-authored-by: Erich Keane <ekeane at nvidia.com>
Commit: 93df3e81665427e4eb3f1be60848d6d27a311897
https://github.com/llvm/llvm-project/commit/93df3e81665427e4eb3f1be60848d6d27a311897
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A llvm/test/Analysis/BasicAA/call.ll
Log Message:
-----------
[BasicAA] Add additional test for call AA (NFC)
Commit: 7b3455e24ab5aa090e5b2b9ce50c249843c45754
https://github.com/llvm/llvm-project/commit/7b3455e24ab5aa090e5b2b9ce50c249843c45754
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/unittests/API/SBCommandInterpreterTest.cpp
Log Message:
-----------
[lldb] Fix double free in CommandPluginInterfaceImplementation (#131658)
The class was taking ownership of the SBCommandPluginInterface pointer
it was passed in, by wrapping it in a shared pointer. This causes a
double free in the unit test when the object is destroyed and the same
pointer gets freed once when the SBCommandPluginInterface goes away and
then again when the shared pointer hits a zero refcount.
Commit: 1ae307a709f81e57356cd135f6a30c3c6174cd70
https://github.com/llvm/llvm-project/commit/1ae307a709f81e57356cd135f6a30c3c6174cd70
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A clang/test/CIR/Tools/cir-translate-triple.cir
A clang/test/CIR/Tools/has-triple-and-data-layout.cir
A clang/test/CIR/Tools/has-triple-no-data-layout.cir
A clang/test/CIR/Tools/invalid-translate-triple.cir
A clang/test/CIR/Tools/no-triple-has-data-layout.cir
A clang/test/CIR/Tools/no-triple-no-data-layout.cir
A clang/test/CIR/Tools/warn-default-triple.cir
M clang/tools/CMakeLists.txt
A clang/tools/cir-lsp-server/CMakeLists.txt
A clang/tools/cir-lsp-server/cir-lsp-server.cpp
A clang/tools/cir-translate/CMakeLists.txt
A clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[CIR] Add cir-translate and cir-lsp-server tools (#131181)
Adds two new clang tools to the tree.
* cir-translate: Translates CIR to LLVM, similar to mlir-translate
* cir-lsp-server: Implementation of the Language Server Protocol for
ClangIR, similar to fir-lsp-server
---------
Co-authored-by: Morris Hafner <mhafner at nvidia.com>
Commit: 24fbf9dd428dc0a571ccd28e730f0411ef6c5ff8
https://github.com/llvm/llvm-project/commit/24fbf9dd428dc0a571ccd28e730f0411ef6c5ff8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/arith-ssat-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-ssat-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-ssat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-ssat.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-usat.ll
Log Message:
-----------
[CostModel][X86] merge saturated arithmetic costs tests using -cost-kind=all (#131828)
Commit: d43b4ede6649e4ecf650a4660f62840e95043898
https://github.com/llvm/llvm-project/commit/d43b4ede6649e4ecf650a4660f62840e95043898
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-linkage-intrinsic-global-variables.ll
M llvm/tools/llvm-reduce/deltas/ReduceGlobalValues.cpp
Log Message:
-----------
llvm-reduce: Do not remove appending linkage from intrinsic globals (#131713)
Commit: 6d38dbf6eb56fd2b3399565af455de96a99ffa0f
https://github.com/llvm/llvm-project/commit/6d38dbf6eb56fd2b3399565af455de96a99ffa0f
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/test/API/functionalities/reverse-execution/TestReverseContinueBreakpoints.py
M lldb/test/API/functionalities/reverse-execution/TestReverseContinueWatchpoints.py
Log Message:
-----------
[lldb] Skip reverse continue tests on macos<15.0
They're failing for unknown reasons.
Commit: 84909d797782a0dcf240f79a8e5e863d8165c03f
https://github.com/llvm/llvm-project/commit/84909d797782a0dcf240f79a8e5e863d8165c03f
Author: Julian Brown <julian.brown at amd.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
A llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
Log Message:
-----------
[AMDGCN] Allow unscheduling of bundled insns
This is a patch arising from AMD's fuzzing project.
In the test case, the scheduling algorithm decides to undo an attempted
schedule, but is unprepared to handle bundled instructions at that
point -- and those can arise via the expansion of intrinsics earlier
in compilation. The fix is to use the splice method instead of
remove/insert, since that can handle bundles properly.
Commit: 45090b3059562b32723cd25679db75d1574ab04e
https://github.com/llvm/llvm-project/commit/45090b3059562b32723cd25679db75d1574ab04e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
Log Message:
-----------
[SLP]Check the whole def-use chain in the tree to find proper dominance, if the last instruction is the same
If the insertion point (last instruction) of the user nodes is the same,
need to check the whole def-use chain in the tree to find proper
dominance to prevent a compiler crash.
Fixes #131818
Commit: 6c7c660afe0ccddcd1bac0c153280d105d04590f
https://github.com/llvm/llvm-project/commit/6c7c660afe0ccddcd1bac0c153280d105d04590f
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Clauses.cpp
Log Message:
-----------
[flang] Use C-style casts to silence message (NFC) (#131796)
Commit: b271b44158804256a982fe8b2c5edbdba3a0bf15
https://github.com/llvm/llvm-project/commit/b271b44158804256a982fe8b2c5edbdba3a0bf15
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/include/__mutex/once_flag.h
M libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp
M libcxx/test/support/operator_hijacker.h
Log Message:
-----------
[libc++] Guard call_once against operator hijacking. (#128054)
Commit: 76a9d792d93990bb24a6e2e17a204000f3a0d572
https://github.com/llvm/llvm-project/commit/76a9d792d93990bb24a6e2e17a204000f3a0d572
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/include/__functional/function.h
M libcxx/include/__numeric/gcd_lcm.h
M libcxx/include/__numeric/saturation_arithmetic.h
M libcxx/include/locale
Log Message:
-----------
[NFC][libc++] Guard against operator& hijacking. (#129453)
Commit: 168177a0bd009269bec4d752b8096c63c492af76
https://github.com/llvm/llvm-project/commit/168177a0bd009269bec4d752b8096c63c492af76
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/arith-sminmax-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-sminmax-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-sminmax-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-sminmax.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-uminmax.ll
Log Message:
-----------
[CostModel][X86] merge arithmetic integer min/max costs tests using -cost-kind=all (#131834)
Commit: 04ab8a5fba71f7ec65634cc118dc13798a9037fc
https://github.com/llvm/llvm-project/commit/04ab8a5fba71f7ec65634cc118dc13798a9037fc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/src/stdio/scanf_core/vfscanf_internal.h
Log Message:
-----------
[libc] Fix the GPU build after scanf rework
Summary:
Needs these to be included.
Commit: 1a9521565019edc8589f234c95477ab0a6b164d5
https://github.com/llvm/llvm-project/commit/1a9521565019edc8589f234c95477ab0a6b164d5
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/int64ops.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/propagate-function-flags-test.ll
Log Message:
-----------
[DirectX] Set function-level flag Int64Ops in DXIL Shader Flags Analysis (#129089)
Fixes #114562
Commit: d3bcbd6b32bfee6e924397e704fcf2a94659af6b
https://github.com/llvm/llvm-project/commit/d3bcbd6b32bfee6e924397e704fcf2a94659af6b
Author: john-stuart2 <john.stuart.science at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
Log Message:
-----------
[Docs] Fix concat vectors (#131860)
GenericOpcodes.td states that the number of operands are variadic.
let InOperandList = (ins type1:$src0, variable_ops);
X86 supports up to 4 inputs. The example uses 512-bit aka AVX-512 to
make it look real and show the effect of the ~many operands.
Test plan: ninja docs-llvm-html
Commit: 40c6f8984126407569b9b86f11050046950a4b3e
https://github.com/llvm/llvm-project/commit/40c6f8984126407569b9b86f11050046950a4b3e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
Log Message:
-----------
[CostModel][X86] merge fp arithmetic costs tests using -cost-kind=all (#131839)
Commit: a5a9b2b92ff02d9b95e43af9f4fcf4c3823333b2
https://github.com/llvm/llvm-project/commit/a5a9b2b92ff02d9b95e43af9f4fcf4c3823333b2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/arith-int-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-int-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-int-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-int.ll
Log Message:
-----------
[CostModel][X86] merge integer arithmetic costs tests using -cost-kind=all (#131840)
Commit: 9feac2cbd0d80927ce9a8b4c3e810d2b81802d55
https://github.com/llvm/llvm-project/commit/9feac2cbd0d80927ce9a8b4c3e810d2b81802d55
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libcxx/include/__functional/binary_function.h
M libcxx/include/__functional/unary_function.h
M libcxx/include/__functional/weak_result_type.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/types.pass.cpp
Log Message:
-----------
[libc++] Improve deprecated diagnostic guards.
Recent Clang-21 builds improved the deprecated diagnotics. This
uncovered missing guards in libc++ internally.
Note: This patch should be a separate commit and not merged.
For testing purposes they are combined.
Reviewed as part of #130497.
Commit: dbc7665b24eca1568902808bfb05db4b752cad19
https://github.com/llvm/llvm-project/commit/dbc7665b24eca1568902808bfb05db4b752cad19
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll
M llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
M llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/mma-outer-product.ll
M llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
Log Message:
-----------
PowerPC: Use REG_SEQUENCE instead of INSERT_SUBREG (#129941)
Update to use REG_SEQUENCE when possible.
This patch only update td pattern to utilize REG_SEQUENCE for
INSERT_SUBREG for cases where it does not produce
a nesting of REG_SEQUENCE. This seem to show some improvement in code
gen for `llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll`.
Fixes part of https://github.com/llvm/llvm-project/issues/125502
Commit: b326cb6792b3951881d63d5a02ea163921da18d9
https://github.com/llvm/llvm-project/commit/b326cb6792b3951881d63d5a02ea163921da18d9
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-icmp-and.ll
Log Message:
-----------
[InstCombine] Support trunc to i1 in foldSelectICmpAnd (#127905)
proof: https://alive2.llvm.org/ce/z/Ey6BoT
Commit: 19970535f92c0f2dcda01b7fc60f95945166e424
https://github.com/llvm/llvm-project/commit/19970535f92c0f2dcda01b7fc60f95945166e424
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Log Message:
-----------
[PowerPC] Avoid repeated hash lookups (NFC) (#131724)
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: e6c3d94915f55cf01b0a29266f0ea9881b4676f7
https://github.com/llvm/llvm-project/commit/e6c3d94915f55cf01b0a29266f0ea9881b4676f7
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
Log Message:
-----------
[InstCombine] Add test for foldSelectICmpAndBinOp with range attribute. (NFC)
Commit: 8cc9a485792240314ad723dcf6661490850d2c98
https://github.com/llvm/llvm-project/commit/8cc9a485792240314ad723dcf6661490850d2c98
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/Sema/aarch64-sve-vector-exp-ops.c
M clang/test/Sema/aarch64-sve-vector-log-ops.c
M clang/test/Sema/aarch64-sve-vector-pow-ops.c
M clang/test/Sema/aarch64-sve-vector-trig-ops.c
M clang/test/Sema/builtins-elementwise-math.c
M clang/test/Sema/builtins-reduction-math.c
M clang/test/Sema/count-builtins.c
M clang/test/Sema/riscv-rvv-vector-exp-ops.c
M clang/test/Sema/riscv-rvv-vector-log-ops.c
M clang/test/Sema/riscv-rvv-vector-trig-ops.c
M clang/test/Sema/riscv-sve-vector-pow-ops.c
M clang/test/SemaHLSL/BuiltIns/clamp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/exp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/firstbithigh-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/firstbitlow-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/lerp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/mad-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/reversebits-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/round-errors.hlsl
Log Message:
-----------
[clang] Improve diagnostics for vector builtins (#125673)
This commit improves the diagnostics for vector (elementwise) builtins
in a couple of ways.
It primarily provides more precise type-checking diagnostics for
builtins with specific type requirements. Previously many builtins were
receiving a catch-all diagnostic suggesting types which aren't valid.
It also makes consistent the type-checking behaviour between various
binary and ternary builtins. The binary builtins would check for
mismatched argument types before specific type requirements, whereas
ternary builtins would perform the checks in the reverse order. The
binary builtins now behave as the ternary ones do.
Commit: 14c95e0c8b25f6deba47cd279c5dcdeef3870159
https://github.com/llvm/llvm-project/commit/14c95e0c8b25f6deba47cd279c5dcdeef3870159
Author: Wael Yehia <wmyehia2001 at yahoo.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPort.h
M compiler-rt/lib/profile/InstrProfilingUtil.c
M compiler-rt/lib/profile/InstrProfilingUtil.h
M compiler-rt/test/profile/Posix/instrprof-fork.c
A compiler-rt/test/profile/instrprof-no-mmap-during-merging.c
Log Message:
-----------
[profile] Implement a non-mmap path when reading profile files from a non-local filesystem (#131177)
On AIX, when accessing mmap'ed memory associated to a file on NFS, a
SIGBUS might be raised at random.
The problem is still in open state with the OS team.
This PR teaches the profile runtime, under certain conditions, to avoid
the mmap when reading the profile file during online merging.
This PR has no effect on any platform other than AIX because I'm not
aware of this problem on other platforms.
Other platforms can easily opt-in to this functionality in the future.
The logic in function `is_local_filesystem` was copied from
[llvm/lib/Support/Unix/Path.inc](https://github.com/llvm/llvm-project/blob/f388ca3d9d9a58e3d189458b590ba68dfd9e5a2d/llvm/lib/Support/Unix/Path.inc#L515)
(https://reviews.llvm.org/D58801), because it seems that the
compiler-rt/profile cannot reuse code from llvm except through
`InstrProfData.inc`.
Thanks to @hubert-reinterpretcast for substantial feedback downstream.
---------
Co-authored-by: Wael Yehia <wyehia at ca.ibm.com>
Co-authored-by: Hubert Tong <hubert.reinterpretcast at gmail.com>
Commit: 123c0040d4e6565091f20c4d6483ae76f1d8f57c
https://github.com/llvm/llvm-project/commit/123c0040d4e6565091f20c4d6483ae76f1d8f57c
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_dl_phdr_info.h
M libc/include/CMakeLists.txt
R libc/include/link.h.def
M libc/include/link.yaml
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__dl_iterate_phdr_callback_t.h
A libc/include/llvm-libc-types/struct_dl_phdr_info.h
M libc/src/CMakeLists.txt
A libc/src/link/CMakeLists.txt
A libc/src/link/dl_iterate_phdr.cpp
A libc/src/link/dl_iterate_phdr.h
M libc/utils/hdrgen/hdrgen/header.py
Log Message:
-----------
[libc] Define (stub) dl_iterate_phdr (#131436)
This fleshes out the <link.h> a little more, including the
`struct dl_phdr_info` type and declaring the dl_iterate_phdr
function. There is only a no-op implementation without tests, as
for the existing dlfcn functions.
Commit: b42f8ec26d5098128b32cc12b5daf342d26fd42e
https://github.com/llvm/llvm-project/commit/b42f8ec26d5098128b32cc12b5daf342d26fd42e
Author: David Green <david.green at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/aggregates.ll
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fp-conversions-odd-vector-types.ll
M llvm/test/Analysis/CostModel/AArch64/fptoi_sat.ll
M llvm/test/Analysis/CostModel/AArch64/load-to-trunc.ll
M llvm/test/Analysis/CostModel/AArch64/logicalop.ll
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-minmax.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll
M llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
M llvm/test/Analysis/CostModel/AArch64/store.ll
M llvm/test/Analysis/CostModel/AArch64/sve-math.ll
M llvm/test/Analysis/CostModel/AArch64/sve-min-max.ll
M llvm/test/Analysis/CostModel/AArch64/vector-reduce.ll
Log Message:
-----------
[AArch64] Update a number of costmodel tests with -cost-kind=all. NFC
Commit: 6313550aced5a611213ac2a551e3a900e8740506
https://github.com/llvm/llvm-project/commit/6313550aced5a611213ac2a551e3a900e8740506
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#131720)
Commit: 460b9cda8109b6978a274e1ea9d762f888b044f6
https://github.com/llvm/llvm-project/commit/460b9cda8109b6978a274e1ea9d762f888b044f6
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
Log Message:
-----------
[libc] Disable dl_iterate_phdr entrypoint for linux fullbuild (#131893)
There are some issues with typedef conflicts between libc headers
and Linux kernel headers arising. Disable building the new code
for Linux for now.
Commit: d039af33096c0a83b03475a240d5e281e2271c44
https://github.com/llvm/llvm-project/commit/d039af33096c0a83b03475a240d5e281e2271c44
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/ErrnoCheckingTest.h
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/unlink_test.cpp
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc] Create ErrnoCheckingTest harness to simplify errno tests. (#131703)
See the discussion in PR
https://github.com/llvm/llvm-project/pull/131650 on why we need to clear
the errno at the beginning of some tests, and outlining the various solutions.
Introduce ErrnoCheckingTest base class and use it for unlink_test as an example.
Commit: fbbb33f4001d24445f0a103f0a5464f129679a76
https://github.com/llvm/llvm-project/commit/fbbb33f4001d24445f0a103f0a5464f129679a76
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Utils/IndexingUtils.cpp
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/transform-op-pack.mlir
Log Message:
-----------
[mlir] Fix crash when verifying linalg.transpose (#131733)
Adds checks in `isPermutationVector` for indices that are outside of the
bounds and removes the assert.
Signed-off-by: Ian Wood <ianwood2024 at u.northwestern.edu>
Commit: 0619892cab8a5cc24e25f7eddcff7316757a1ff0
https://github.com/llvm/llvm-project/commit/0619892cab8a5cc24e25f7eddcff7316757a1ff0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M .ci/metrics/metrics.py
Log Message:
-----------
[CI] Bump max workflow to process count in metrics
This patch bumps the maximum number of metrics to look through when
collecting metrics data. We are currently running into issues where we
are losing data due to the most recent 1000 workflows not containing the
workflows that we actually need to query. Just double it for now.
I plan on monitoring this reasonably closely to ensure we do not run
into issues, mainly API rate limits.
Commit: bc8b19c7575f3882b7655e129d4fc3b74c7fbba3
https://github.com/llvm/llvm-project/commit/bc8b19c7575f3882b7655e129d4fc3b74c7fbba3
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/test/CodeGenCXX/builtins.cpp
M clang/test/CodeGenCXX/mangle.cpp
A clang/test/SemaCXX/builtin-structured-binding-size.cpp
Log Message:
-----------
[Clang] Introduce a trait to determine the structure binding size (#131515)
Introduce a trait to determine the number of bindings that would be
produced by
```cpp
auto [...p] = expr;
```
This is necessary to implement P2300
(https://eel.is/c++draft/exec#snd.concepts-5), but can also be used to
implement a general get<N> function that supports aggregates
`__builtin_structured_binding_size` is a unary type trait that evaluates
to the number of bindings in a decomposition
If the argument cannot be decomposed, a sfinae-friendly error is
produced.
A type is considered a valid tuple if `std::tuple_size_v<T>` is a valid
expression, even if there is no valid `std::tuple_element`
specialization or suitable `get` function for that type.
Fixes #46049
Commit: 4ab011a9502218fc08a609348054307b4a651d83
https://github.com/llvm/llvm-project/commit/4ab011a9502218fc08a609348054307b4a651d83
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/stores-of-loads-merging.ll
Log Message:
-----------
[RISCV] Precommit store merge tests for pr130430
Commit: 7d7b58bc5d2bacc3d76463d2ee06a13d2a08b084
https://github.com/llvm/llvm-project/commit/7d7b58bc5d2bacc3d76463d2ee06a13d2a08b084
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang-rt/lib/runtime/transformational.cpp
M flang-rt/unittests/Runtime/Transformational.cpp
M flang/docs/ArrayRepacking.md
M flang/include/flang/Optimizer/Builder/Runtime/Transformational.h
M flang/include/flang/Runtime/transformational.h
M flang/lib/Optimizer/Builder/Runtime/Transformational.cpp
Log Message:
-----------
[flang-rt] Added ShallowCopy API. (#131702)
This API will be used for copying non-contiguous arrays
into contiguous temporaries to support `-frepack-arrays`.
The builder factory API will be used in the following commits.
Commit: 71f391040969c0dbdf4398a78a742b1a730e2e38
https://github.com/llvm/llvm-project/commit/71f391040969c0dbdf4398a78a742b1a730e2e38
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/test/lit.cfg.py
Log Message:
-----------
[clang][lit] mkdir before mkstemp in is_filesystem_case_insensitive() (#131036)
In the CMake build test_exec_root already exists here, but not in the gn
build, which causes this to fail.
Commit: 592a3ba125e9ff6fccc71084e325c02119523869
https://github.com/llvm/llvm-project/commit/592a3ba125e9ff6fccc71084e325c02119523869
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/sys/utsname.yaml
Log Message:
-----------
[libc][docs] Add sys/utsname header and documentation for uname function (#131817)
These changes tracks `utsname.h` for the implementation status of
functions and macros, with respect to the issue (
https://github.com/llvm/llvm-project/issues/122006 ).
Commit: d51bc835115f707f95acf37396f387b039e6bbc5
https://github.com/llvm/llvm-project/commit/d51bc835115f707f95acf37396f387b039e6bbc5
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Only skip live-ins with constants in materializeBroadccast (NFC)
Currently this should be NFC, but will be needed in future patches.
Commit: 00c5edae173e85067a5db6f49ed6c4778787be55
https://github.com/llvm/llvm-project/commit/00c5edae173e85067a5db6f49ed6c4778787be55
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/stores-of-loads-merging.ll
Log Message:
-----------
[RISCV] Fix typo in test added in 4ab011a95
Let's not talk about how much code I traced through before realizing
the bug was in the test, not the code...
Commit: 1442fe0c897a3a59515c3bf3c8bfe6b4d763b4a8
https://github.com/llvm/llvm-project/commit/1442fe0c897a3a59515c3bf3c8bfe6b4d763b4a8
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
Log Message:
-----------
[LV] Update test to use dereferenceable attribute instead of assumption.
Use dereferenceable attribute instead of assumption to make the tests
independent of https://github.com/llvm/llvm-project/pull/128061.
Commit: c02b935a9be888bbdf9f8cb0bf980bd411ae5893
https://github.com/llvm/llvm-project/commit/c02b935a9be888bbdf9f8cb0bf980bd411ae5893
Author: Jon Chesterfield <jonathanchesterfield at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M offload/DeviceRTL/src/State.cpp
Log Message:
-----------
[openmp][nfc] Refactor shared/lds smartstack for spirv (#131905)
Spirv doesn't have implicit conversions between address spaces (at least
at present, we might need to change that) and address space qualified
*this pointers are not handled well by clang. This commit changes the
single instance of the smartstack to be explicitly a singleton, for
fractionally simpler IR generation (no this pointer) and to sidestep the
work in progress spirv64-- openmp target not being able to compile the
original version.
Commit: 206f78dfec71b86d4f58ef6bf23cc12151f5b54d
https://github.com/llvm/llvm-project/commit/206f78dfec71b86d4f58ef6bf23cc12151f5b54d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/src/Mapping.cpp
Log Message:
-----------
[OpenMP] Use 'gpuintrin.h' definitions for simple block identifiers (#131631)
Summary:
This patch ports the runtime to use `gpuintrin.h` instead of calling the
builtins for most things. The `lanemask_gt` stuff was left for now with
a fallback.
AMD version for Ron
https://gist.github.com/jhuber6/42014d635b9a8158727640876bf47226.
Commit: 395bdebebd23962613e05c296ab608d2b669c649
https://github.com/llvm/llvm-project/commit/395bdebebd23962613e05c296ab608d2b669c649
Author: Jon Chesterfield <jonathanchesterfield at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M offload/DeviceRTL/src/State.cpp
Log Message:
-----------
Revert "[openmp][nfc] Refactor shared/lds smartstack for spirv (#131905)"
This reverts commit c02b935a9be888bbdf9f8cb0bf980bd411ae5893.
Failed a check-offload test under CI
Commit: a65cbc4213ebf263f9e838969fca34f0c72c3f1c
https://github.com/llvm/llvm-project/commit/a65cbc4213ebf263f9e838969fca34f0c72c3f1c
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Darwin/suppressions-sandbox.cpp
Log Message:
-----------
Revert "[Darwin][ASan][Test] Create a noinlined wrapper function for reliable suppression in test. (#131247)"
This reverts commit 78f74f686bfe21262f8b171e21450186edd081ab.
Breaks the test on x86-64 mac, e.g. https://green.lab.llvm.org/job/llvm.org/job/clang-stage1-RA/3852/.
Commit: 056264b838df94b689d3213424d78f8b9452041b
https://github.com/llvm/llvm-project/commit/056264b838df94b689d3213424d78f8b9452041b
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
A clang/include/clang/Tooling/DependencyScanning/InProcessModuleCache.h
M clang/lib/Tooling/DependencyScanning/CMakeLists.txt
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/lib/Tooling/DependencyScanning/InProcessModuleCache.cpp
Log Message:
-----------
[clang][deps] Implement efficient in-process `ModuleCache` (#129751)
The dependency scanner uses implicitly-built Clang modules under the
hood. This system was originally designed to handle multiple concurrent
processes working on the same module cache, and mutual exclusion was
implemented using file locks. The scanner, however, runs within single
process, making file locks unnecessary. This patch virtualizes the
interface for module cache locking and provides an implementation based
on `std::shared_mutex`. This reduces `clang-scan-deps` runtime by ~17%
on my benchmark.
Note that even when multiple processes run a scan on the same module
cache (and therefore don't coordinate efficiently), this should still be
correct due to the strict context hash, the write-through
`InMemoryModuleCache` and the logic for rebuilding out-of-date or
incompatible modules.
Commit: d32c6dd9be6c243a2891cd9b5149f71da465aed0
https://github.com/llvm/llvm-project/commit/d32c6dd9be6c243a2891cd9b5149f71da465aed0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
Log Message:
-----------
[RISCV] Use MnemonicAlias for 'fssr' and 'frsr'. NFC (#131877)
Commit: bc646f4b302339717e363efa3e57ec3468d190aa
https://github.com/llvm/llvm-project/commit/bc646f4b302339717e363efa3e57ec3468d190aa
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Tooling/DependencyScanning/BUILD.gn
Log Message:
-----------
[gn build] Port 056264b838df
Commit: 70bf5e514b21b34b01fb572428f8fbdf267d5c3b
https://github.com/llvm/llvm-project/commit/70bf5e514b21b34b01fb572428f8fbdf267d5c3b
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.h
A bolt/test/AArch64/got-load-symbolization.s
Log Message:
-----------
[BOLT][AArch64] Symbolize ADRP after relaxation (#131414)
When the linker relaxes a GOT load, it changes ADRP+LDR instruction pair
into ADRP+ADD. It is relatively straightforward to detect and symbolize
the second instruction in the disassembler. However, it is not always
possible to properly symbolize the ADRP instruction without looking at
the second instruction. Hence, we have the FixRelaxationPass that adjust
the operand of ADRP by looking at the corresponding ADD.
This PR tries to properly symbolize ADRP earlier in the pipeline, i.e.
in AArch64MCSymbolizer. This change makes it easier to adjust the
instruction once we add AArch64 support in `scanExternalRefs()`.
Additionally, we get a benefit of looking at proper operands while
observing the function state prior to running FixRelaxationPass.
To disambiguate the operand of ADRP that has a GOT relocation against
it, we look at the contents/value of the operand. If it contains an
address of a page that is valid for GOT, we assume that the operand
wasn't modified by the linker and leave it up to FixRelaxationPass to do
a proper adjustment. If the page referenced by ADRP cannot point to GOT,
then it's an indication that the linker has modified the operand and we
substitute the operand with a non-GOT reference to the symbol.
Commit: deb0f3c09b77cebe01976539e2d5f07964e2dc2a
https://github.com/llvm/llvm-project/commit/deb0f3c09b77cebe01976539e2d5f07964e2dc2a
Author: Jon Chesterfield <jonathanchesterfield at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M offload/DeviceRTL/src/State.cpp
M offload/include/Shared/Utils.h
Log Message:
-----------
[openmp][nfc] Use builtin align in the devicertl (#131918)
Noticed while extracting the smartstack as a test case
Commit: 934ef305227ad4bd3d95c92e0f9cf1ad605ced9d
https://github.com/llvm/llvm-project/commit/934ef305227ad4bd3d95c92e0f9cf1ad605ced9d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/lib/Tooling/DependencyScanning/InProcessModuleCache.cpp
Log Message:
-----------
[clang] Fix warnings
This patch fixes:
clang/lib/Tooling/DependencyScanning/InProcessModuleCache.cpp:38:5:
error: 'shared_lock' may not intend to support class template
argument deduction [-Werror,-Wctad-maybe-unsupported]
clang/lib/Tooling/DependencyScanning/InProcessModuleCache.cpp:68:7:
error: 'lock_guard' may not intend to support class template
argument deduction [-Werror,-Wctad-maybe-unsupported]
Commit: e6896f80da0d094518fce54b0fe1238f0f2c9a41
https://github.com/llvm/llvm-project/commit/e6896f80da0d094518fce54b0fe1238f0f2c9a41
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/MC/RISCV/rvzfh-aliases-valid.s
Log Message:
-----------
[RISCV] Remove unnecessary alias tests from rvzfh-aliases-valid.s. NFC
These are testing fmv.x.h and fmv.h.x which aren't aliases. This
appears to have been incorrectly copied from rvf-aliases-valid.s
where fmv.x.s and fmv.s.x are aliases for fmv.x.w and fmv.w.x.
Commit: 187277474a789b9dd1ef7aeeeb90d315a60c6e8b
https://github.com/llvm/llvm-project/commit/187277474a789b9dd1ef7aeeeb90d315a60c6e8b
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
Log Message:
-----------
[clang][deps] Fix build after #129751
Some compilers don't like having a member variable name that shadows the type name.
Commit: 2203caf860418b9ecbed8b0b205c5265ae7b4743
https://github.com/llvm/llvm-project/commit/2203caf860418b9ecbed8b0b205c5265ae7b4743
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Update C++ DR status page (#131812)
CWG472 is one of the CWG issues that were assigned to Mike Miller with
`drafting` status, but recently got back to `open`, because Mike is no
longer active in CWG. Nothing to be done here, except for changing the
status.
CWG1432 was recently reopened after a CWG reflector discussion. I
changed the status to claim that we test for the previous resolution.
Commit: a6c09d40ed7fe076358429c0978838904c9cceae
https://github.com/llvm/llvm-project/commit/a6c09d40ed7fe076358429c0978838904c9cceae
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/div-codesize.ll
R llvm/test/Analysis/CostModel/X86/div-latency.ll
R llvm/test/Analysis/CostModel/X86/div-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/div.ll
R llvm/test/Analysis/CostModel/X86/rem-codesize.ll
R llvm/test/Analysis/CostModel/X86/rem-latency.ll
R llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
Log Message:
-----------
[CostModel][X86] merge integer div/rem costs tests using -cost-kind=all (#131873)
Commit: a21dd255ad79442a847581e3f06900ba0a534a49
https://github.com/llvm/llvm-project/commit/a21dd255ad79442a847581e3f06900ba0a534a49
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/www/make_cxx_dr_status
Log Message:
-----------
[clang] Enforce UTF-8 in `make_cxx_dr_status` (#131816)
Otherwise Windows users have troubles with lexer tests that use emojis.
Commit: 7d4332a8f96483c02f853c353d475b2e445d0f79
https://github.com/llvm/llvm-project/commit/7d4332a8f96483c02f853c353d475b2e445d0f79
Author: thetruestblue <bblueconway at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M compiler-rt/test/asan/lit.cfg.py
Log Message:
-----------
[Darwin][Test][leaks] Disable leak detection for asan tests on non-Intel Darwin devices (#131676)
`detect_leaks` option for asan does not work well on Apple Silicon
(arm64) MacOS devices and results in hundreds of ASan test failures when
run with this option set for all tests.
We should not add this option for tests unless we are targeting an
x86_64 device for Darwin, where this seems to be tested and working
well.
rdar://147069153
Commit: 2b7c729e34b1522a737f718c492bf18cdbcd5f60
https://github.com/llvm/llvm-project/commit/2b7c729e34b1522a737f718c492bf18cdbcd5f60
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
R llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
Log Message:
-----------
[RISCV] Normalize test naming and layout for shuffle tests [NFC]
Commit: 93b8ef463a071d6057bc826fd244e94e8361518e
https://github.com/llvm/llvm-project/commit/93b8ef463a071d6057bc826fd244e94e8361518e
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
Log Message:
-----------
[RISCV] Split and expand test coverage for zipeven/zipodd shuffles [NFC]
Commit: 8a91f6bcda4536a866e2e0b596687ecd19ceeef5
https://github.com/llvm/llvm-project/commit/8a91f6bcda4536a866e2e0b596687ecd19ceeef5
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Use CurrentParentLoop instead of looking up via CFG (NFC).
There is no need to look up the current parent loop via LoopInfo and the
vector preheader; we can simply use CurrentParentLoop.
Commit: 870f753f1f5e67aebccb46b158083a6c45bebce6
https://github.com/llvm/llvm-project/commit/870f753f1f5e67aebccb46b158083a6c45bebce6
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
Log Message:
-----------
[VPlan] Also materialize broadcasts for backedge-taken-counts (NFC).
Also include VPlan's BTC in the set of VPValues to materialize
broadcasts for, if it is used.
Commit: 98943c4bd84e61ecb2bf79983baa7138e8db7fed
https://github.com/llvm/llvm-project/commit/98943c4bd84e61ecb2bf79983baa7138e8db7fed
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/admin.c
Log Message:
-----------
[ARM,MVE] Change placeholder from `undef` to `poison` (#131689)
Call `insertelement` on a `poison` value instead of `undef`.
Commit: b7ed5c8e06221d66ee69036e24a079ee3f528a99
https://github.com/llvm/llvm-project/commit/b7ed5c8e06221d66ee69036e24a079ee3f528a99
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Support/Fortran.cpp
M flang/test/Semantics/cuf13.cuf
Log Message:
-----------
[flang][cuda] Check for ignore_tkr(d) when resolving generic call (#131923)
Commit: bb0cc6948725b8030069c07aeff1fe6abd8fa027
https://github.com/llvm/llvm-project/commit/bb0cc6948725b8030069c07aeff1fe6abd8fa027
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
Log Message:
-----------
[webkit.NoUncountedMemberChecker] Fix a regression that every class is treated as if it's ref countable. (#131249)
This PR fixes a regression that webkit.NoUncountedMemberChecker and
alpha.webkit.NoUncheckedMemberChecker emits warnings for every class as
if they supported ref counting and checked ptr because we were
erroneously coercing the return value of isRefCountable and
isCheckedPtrCapable, which is std::optional<bool>, to boolean values.
Commit: 43c21f96a7626364054109af5aa4e84bf537c1c5
https://github.com/llvm/llvm-project/commit/43c21f96a7626364054109af5aa4e84bf537c1c5
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M .ci/compute-projects.sh
M .ci/generate-buildkite-pipeline-premerge
M .ci/monolithic-linux.sh
M flang-rt/README.md
Log Message:
-----------
Revert "[Premerge] Add flang-rt (#128678)" (#131915)
This reverts commit 95d28fe503cc3d2bc0bb980442d3defaf199ea5a.
I did not fully realize the implications of this change when reviewing.
With how it is set up currently, it causes clang and all of the runtimes
to be built and tested everytime a change to MLIR is made. This is a
large regression in build/test time, which seems to have been causing
large queueing delays.
Reverting for now. Once we rework the runtimes build for premerge (which
I hope to do soon, ideally in the next week), I will make sure flang-rt
gets added in.
Commit: b251c29af45d3440374f53bb4c1645e5968593f7
https://github.com/llvm/llvm-project/commit/b251c29af45d3440374f53bb4c1645e5968593f7
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
Log Message:
-----------
[mlir][tosa] Update PadOp examples in the dialect description (#131919)
* pad_const is now required for tosa.pad op after
PR[@129336](https://github.com/llvm/llvm-project/pull/129336)
* updated the examples in the dialect description section to reflect
this change.
Signed-off-by: Jerry Ge <jerry.ge at arm.com>
Commit: 0e4116a6b999058a96710d598d2384075185f2c9
https://github.com/llvm/llvm-project/commit/0e4116a6b999058a96710d598d2384075185f2c9
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
Log Message:
-----------
[AMDGPU] Fix typing error in multi dimensional promote alloca (#131763)
Fix type error when GEP uses i64 index introduced in #127973.
Commit: 7a9473b1b0b8bdfd5f3fcae578ddcca5b49d8803
https://github.com/llvm/llvm-project/commit/7a9473b1b0b8bdfd5f3fcae578ddcca5b49d8803
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang-rt/lib/runtime/transformational.cpp
Log Message:
-----------
[flang-rt] Fixed build issue in flang-runtime-cuda-clang.
Commit: 854a4f2bbb06ba11fc45b6423ba470d07f247b20
https://github.com/llvm/llvm-project/commit/854a4f2bbb06ba11fc45b6423ba470d07f247b20
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M libcxx/include/__algorithm/inplace_merge.h
M libcxx/include/algorithm
M libcxx/test/std/algorithms/alg.sorting/alg.merge/inplace_merge.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.merge/inplace_merge_comp.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
A libcxx/test/support/constexpr_random.h
M libcxx/test/support/counting_predicates.h
Log Message:
-----------
[libc++] Implement part of P2562R1: constexpr `std::inplace_merge` (#129008)
Drive-by:
- Adds `constexpr_random.h` for pseudo-randomizing or shuffling in tests
for constant evaluation.
Commit: 9ed772cecc23f5f5b060720399b010275bbb7457
https://github.com/llvm/llvm-project/commit/9ed772cecc23f5f5b060720399b010275bbb7457
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Transforms/debug-dummy-argument.fir
Log Message:
-----------
[flang] Fixed computation of position of function's arg in AddDebugInfo. (#131672)
I am working on `-frepack-array` feature (#127147), which produces
non-trivial manipulations with arguments of `fir.declare`.
In this case, we end up with CFG computation of the `fir.declare`
argument, and AddDebugInfo pass incorrectly mapped two dummy arguments
to the same arg index in the debug attributes.
This patch makes sure that we assign the arg index only if we can prove
that we've traced the block argument to the function's entry block.
I believe this problem is not specific to `-frepack-arrays`, e.g.
it may appear due to MLIR inlining as well.
Commit: af7c8c475ab97382a466bce8ad2fd091e0e09c1e
https://github.com/llvm/llvm-project/commit/af7c8c475ab97382a466bce8ad2fd091e0e09c1e
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/search.yaml
M libc/src/search/CMakeLists.txt
M libc/src/search/lfind.cpp
A libc/src/search/lsearch.cpp
A libc/src/search/lsearch.h
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/lsearch_test.cpp
Log Message:
-----------
[libc] Implement `search/lsearch` (#131431)
ref:
- https://man7.org/linux/man-pages/man3/lsearch.3.html
- https://pubs.opengroup.org/onlinepubs/009696699/functions/lsearch.html
Commit: d2c41fb85d960e094a16686fb0ff67d9a2f01d8d
https://github.com/llvm/llvm-project/commit/d2c41fb85d960e094a16686fb0ff67d9a2f01d8d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/MC/RISCV/rv32i-invalid.s
A llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s
M llvm/test/MC/RISCV/rvzfh-pseudos.s
A llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s
Log Message:
-----------
[RISCV] Correct the predicates for the flh/fsh InstAlias and assembler pseudos to include Zfbfmin. (#131920)
Commit: fbc1038f0cfe4038d412914cfd8b2ee4a48bba45
https://github.com/llvm/llvm-project/commit/fbc1038f0cfe4038d412914cfd8b2ee4a48bba45
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
Log Message:
-----------
[mlir][TosaToLinalg] Only support ranked tensor for `reduce` and `gather` (#131805)
This PR adds checks for ranked tensors in converter of reduce and gather
to prevent crash. Fixes #131087.
Commit: ecae8d0f77e94504c186086720fd40a8549ba138
https://github.com/llvm/llvm-project/commit/ecae8d0f77e94504c186086720fd40a8549ba138
Author: john-stuart2 <john.stuart.science at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
Log Message:
-----------
[Docs] Add more vector examples (#131887)
The order of parameters is derived from GenericOpcodes.td. I wanted to
keep the examples separate from the fix.
Commit: 6f44be97d035c7c050e5ee4081154a8441a2a137
https://github.com/llvm/llvm-project/commit/6f44be97d035c7c050e5ee4081154a8441a2a137
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/test/CodeGen/fake-use-determinism.c
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
Log Message:
-----------
IR: Make llvm.fake.use a DefaultAttrsIntrinsic (#131743)
This shouldn't be special and is just an ordinary sideeffect.
Commit: 2e39533e5055bc82bf5a1b2a888e5d65a33e72f9
https://github.com/llvm/llvm-project/commit/2e39533e5055bc82bf5a1b2a888e5d65a33e72f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
Log Message:
-----------
AMDGPU: Fix broken check prefix and degraded cov4 test coverage (#131757)
Commit: a274ea1e3a3e1a824e876732074e4638e197b076
https://github.com/llvm/llvm-project/commit/a274ea1e3a3e1a824e876732074e4638e197b076
Author: ming <99472920+yanming123456 at users.noreply.github.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
Log Message:
-----------
[RISCV] Call SimplifyDemandedBits on the scalar input of vmv_s_x_vl (#131711)
The vmv.s.x instruction copies the scalar integer register to element 0
of the destination vector register. If SEW < XLEN, the least-significant
bits are copied and the upper XLEN-SEW bits are ignored.
Co-authored-by: yanming <ming.yan at terapines.com>
Commit: 04e39ce3fddaaec41d9c7babcca55133d7e49969
https://github.com/llvm/llvm-project/commit/04e39ce3fddaaec41d9c7babcca55133d7e49969
Author: Vy Nguyen <vyng at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/include/lldb/Core/Telemetry.h
M lldb/source/Core/Telemetry.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
Log Message:
-----------
[LLDB][Telemetry]Define TargetInfo for collecting data about a target (#127834)
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: 40885572783b1b1d3fe5dc7bce119f08728dc11f
https://github.com/llvm/llvm-project/commit/40885572783b1b1d3fe5dc7bce119f08728dc11f
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
Log Message:
-----------
[lldb-dap] Move request capabilities into request handlers (NFC) (#131943)
This distributes the registration of request related capabilities to the
corresponding request handler. Global and unsupported capabilities are
registered at the DAP level.
Commit: 1028ea9e2641341436555347fb65d6f2eafcfbdd
https://github.com/llvm/llvm-project/commit/1028ea9e2641341436555347fb65d6f2eafcfbdd
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/RequestHandler.h
Log Message:
-----------
[lldb-dap] RequestHandler::getCommand -> RequestHandler::GetCommand (NFC)
Chang the capitalization of getCommand to comply with LLDB's code style.
Commit: 193866bc243ec466a6354a6c5d8ad8193157fe90
https://github.com/llvm/llvm-project/commit/193866bc243ec466a6354a6c5d8ad8193157fe90
Author: Krzysztof Drewniak <krzysdrewniak at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/TableGen/Record.cpp
A llvm/test/TableGen/isa-non-primary.td
Log Message:
-----------
[tblgen] Fix behavior of !isa to prevent premature folding (#130442)
The test included with this commit shows a case where, even though a
record's true type was !isa<> some unrelated class, the isa<> operator
wolud use the declared type of the argument it was examining in order to
conclude that the !isa<> expression had to be be false.
The issues is fixed by checking to make sure that the argument to the
!isa operator is fully concrete before declaring its result to be false.
Commit: 428e3a27c35935197bb7b832dacb8fa468b4bc59
https://github.com/llvm/llvm-project/commit/428e3a27c35935197bb7b832dacb8fa468b4bc59
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
Log Message:
-----------
AMDGPU: Fix attributor not handling all trap intrinsics (#131758)
Commit: 5ac680c5bffdc216d131fd260d2b1c9435b15571
https://github.com/llvm/llvm-project/commit/5ac680c5bffdc216d131fd260d2b1c9435b15571
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
AMDGPU: Add more freeze codegen tests (#131843)
Commit: 6cc23faaac28cc2b8aa0f6e64bfb92cceeaf4958
https://github.com/llvm/llvm-project/commit/6cc23faaac28cc2b8aa0f6e64bfb92cceeaf4958
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
Log Message:
-----------
[AMDGPU][NPM] Port AMDGPUMarkLastScratchLoad to NPM (#131738)
This finishes all passes for the optimized regalloc path.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 3c8c2914e067e132af951f70d2b3577fe049e19a
https://github.com/llvm/llvm-project/commit/3c8c2914e067e132af951f70d2b3577fe049e19a
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
Log Message:
-----------
[NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (#131371)
When the sift amount of a 64-bit funnel-shift or rotate is constant, it
may be decomposed into two 32-bit funnel-sifts. This ensures that we
recover any possible performance losses associated with the correctness
fix in a131fbf1.
In order to efficiently represent the expansion with Selection DAG
nodes, NVPTXISD::BUILD_VECTOR and NVPTXISD::UNPACK_VECTOR are added
which allow the vector output/input to be represented as a scalar. In
the future, if we add support for the v2i32 type to the NVPTX backend
these nodes may be removed.
Commit: b3a4bf9d8f04018bfa81b7e97ec36b247e15b378
https://github.com/llvm/llvm-project/commit/b3a4bf9d8f04018bfa81b7e97ec36b247e15b378
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M libcxx/include/module.modulemap
M libcxx/test/benchmarks/GenerateInput.h
R libcxx/test/benchmarks/algorithms/count.bench.cpp
R libcxx/test/benchmarks/algorithms/equal.bench.cpp
R libcxx/test/benchmarks/algorithms/find.bench.cpp
R libcxx/test/benchmarks/algorithms/for_each.bench.cpp
R libcxx/test/benchmarks/algorithms/mismatch.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/adjacent_find.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/any_all_none_of.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/contains.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/contains_subrange.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/count.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/ends_with.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/equal.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_end.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_first_of.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_last.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/fold.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/for_each.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/is_permutation.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/mismatch.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/search.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/starts_with.bench.cpp
R libcxx/test/benchmarks/algorithms/ranges_contains.bench.cpp
R libcxx/test/benchmarks/algorithms/ranges_ends_with.bench.cpp
Log Message:
-----------
[libc++] Refactor and add benchmarks from [alg.nonmodifying] (#128206)
Commit: fd0e20a64bde212c20c269e7c1349d703e8159d5
https://github.com/llvm/llvm-project/commit/fd0e20a64bde212c20c269e7c1349d703e8159d5
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M flang/include/flang/Lower/ConvertVariable.h
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Lower/ConvertVariable.cpp
A flang/test/Lower/repack-arrays.f90
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang] Generate fir.pack/unpack_array in Lowering. (#131704)
Basic generation of array repacking operations in Lowering.
Commit: 1757a235e386be908d5df01bb736085270d31686
https://github.com/llvm/llvm-project/commit/1757a235e386be908d5df01bb736085270d31686
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.h
M compiler-rt/lib/ctx_profile/tests/CtxInstrProfilingTest.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll
Log Message:
-----------
[ctxprof] Make ContextRoot an implementation detail (#131416)
`ContextRoot` `FunctionData` are currently known by the llvm side, which has to instantiate and zero-initialize them.
This patch makes `FunctionData` the only global value that needs to be known and instantiated by the compiler. On the compiler-rt side, `ContextRoot`s are hung off `FunctionData`, when applicable.
This is for two reasons. First, it is a step towards root autodetection (in a subsequent patch). An autodetection mechanism would instantiate the `ContextRoot` for the detected roots, and then `__llvm_ctx_profile_get_context` would detect that and route to `__llvm_ctx_profile_start_context`.
The second reason is that we will hang off `ContextRoot` more complex datatypes (next patch), and we want to avoid too deep of a coupling between llvm and compiler-rt. Acting as a place to hang related data, `FunctionData` can stay simple - pointers and an (atomic) int (the mutex).
Commit: 35cd6a4c116b28405d814f571540819b08bc83f6
https://github.com/llvm/llvm-project/commit/35cd6a4c116b28405d814f571540819b08bc83f6
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
Log Message:
-----------
[RISCV] Sink NOT to be fold into ANDN/ORN/XNOR/VANDN (#131632)
Undoes a negation being hoisted out of a loop, so that it can be fold
into an inverted bitwise operation in the loop.
Implements #108840 on RISC-V
Commit: fa1228552fd85a8d989d7ac42afa270cc1e371ec
https://github.com/llvm/llvm-project/commit/fa1228552fd85a8d989d7ac42afa270cc1e371ec
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/test/MC/X86/abs8.s
Log Message:
-----------
[X86] Move ABS8 special case to fixupNeedsRelaxationAdvanced
And add a test that X86MCCodeEmitter doesn't utilize a 1-byte
immediate for `cmp (3+$foo)@ABS8, %edi`
Commit: 4e4e4a190fb7c74453994935c843b09cc682f4bb
https://github.com/llvm/llvm-project/commit/4e4e4a190fb7c74453994935c843b09cc682f4bb
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/lib/TextAPI/InterfaceFile.cpp
M llvm/lib/TextAPI/TextStubV5.cpp
A llvm/test/tools/llvm-readtapi/compare-rpath-order.test
M llvm/tools/llvm-readtapi/DiffEngine.cpp
Log Message:
-----------
[TextAPI] Track RPaths in the order its provided via command line. (#131665)
RPaths are basically search paths for how to load dependent libraries.
The order they appear is the order the linker will search, we should
preserve that order in tbd files.
* Additionally add this level of detection to llvm-readtapi.
resolves: rdar://145603347
Commit: 7b00b0b7587120abbab0217c25f23f4e2ba8ae4e
https://github.com/llvm/llvm-project/commit/7b00b0b7587120abbab0217c25f23f4e2ba8ae4e
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
A clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
Log Message:
-----------
[Clang][NFC] Extend cmplx range tests for #131129 (#131447)
- Add tests for complex divdent and real divisor
- Add tests for complex * real multiplication
- Add tests for multiply/divide and assign (`/=`,`*=`) operators
Commit: 57288136fecfac35ef161cb8f147d269715d2634
https://github.com/llvm/llvm-project/commit/57288136fecfac35ef161cb8f147d269715d2634
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M lldb/test/API/functionalities/breakpoint/breakpoint_locations/TestBreakpointLocations.py
Log Message:
-----------
[lldb] Fix TestBreakpointLocations (#131890)
Commit: efc31ecd2773ba378598c86b3a90d038075b9d4e
https://github.com/llvm/llvm-project/commit/efc31ecd2773ba378598c86b3a90d038075b9d4e
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/Transforms/loop-invariant-subset-hoisting.mlir
Log Message:
-----------
[mlir][LICM] Restrict LICM to pure tensor semantics (#129673)
This PR fixes a bug where LICM incorrectly allowed buffer semantics,
which could lead to a crash. Fixes #129416.
Commit: c34dc9a0cf328ace8a68069b1d1bbddd53179053
https://github.com/llvm/llvm-project/commit/c34dc9a0cf328ace8a68069b1d1bbddd53179053
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitCPass.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
A mlir/test/Conversion/SCFToEmitC/scf-to-emitc-failed.mlir
Log Message:
-----------
[mlir][SCFToEmitC] Don't convert unsupported types in EmitC (#131786)
This PR adds check for unsupported types in emitc, which fixes a crash.
Fixes #131442.
Commit: 1bd6716d33e3a4f523058e358a4e84135f64dcf9
https://github.com/llvm/llvm-project/commit/1bd6716d33e3a4f523058e358a4e84135f64dcf9
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/test/CodeGen/cx-complex-range-real.c
Log Message:
-----------
[Clang][CodeGen] Do not promote if complex divisor is real (#131451)
Relates-to: https://github.com/llvm/llvm-project/issues/131129
Commit: f017073cd8ac9e627db17678c6b64e9abe4fbec7
https://github.com/llvm/llvm-project/commit/f017073cd8ac9e627db17678c6b64e9abe4fbec7
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/test/CodeGen/cx-complex-range.c
Log Message:
-----------
[Clang][CodeGen] Promote in complex compound divassign (#131453)
When `-fcomplex-arithmetic=promoted` is set complex divassign `/=` should
promote to a wider type the same way division (without assignment) does.
Prior to this change, Smith's algorithm would be used for divassign.
Fixes: https://github.com/llvm/llvm-project/issues/131129
Commit: 575fde0995aaf60882f433baebf56de2b89195e2
https://github.com/llvm/llvm-project/commit/575fde0995aaf60882f433baebf56de2b89195e2
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
Log Message:
-----------
[AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (#130038)
- Add llvm.amdgcn.image.bvh.dual.intersect.ray intrinsic and
image_bvh_dual_intersect_ray machine instruction.
- Add llvm_v10i32_ty and llvm_v10f32_ty
---------
Co-authored-by: Mateja Marjanovic <mateja.marjanovic at amd.com>
Commit: 125553a6779ba179a9b4b5212c531da2474258fd
https://github.com/llvm/llvm-project/commit/125553a6779ba179a9b4b5212c531da2474258fd
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Add statistics for total LMUL spilled/reloaded (#131747)
The cost of a vector spill/reload may vary highly depending on the size
of the vector register being spilled, i.e. LMUL, so the usual
regalloc.NumSpills/regalloc.NumReloads statistics may not be an accurate
reflection of the total cost.
This adds two new statistics for RISCVInstrInfo that collects the total
number of vector registers spilled/reloaded within groups. It can be
used to get a better idea of regalloc changes in e.g. #131176 #113675
Commit: b5ef33b3b9771c169760bcfa3a72c37b794a4a4c
https://github.com/llvm/llvm-project/commit/b5ef33b3b9771c169760bcfa3a72c37b794a4a4c
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-18 (Tue, 18 Mar 2025)
Changed paths:
M llvm/tools/llvm-objdump/ELFDump.cpp
Log Message:
-----------
[llvm-objdump] Delete unused variables after #128434
Commit: e295f5dd119bf5584174bb3978bbd4ec5f50a0da
https://github.com/llvm/llvm-project/commit/e295f5dd119bf5584174bb3978bbd4ec5f50a0da
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
Log Message:
-----------
[OpenMP][IRBuilder] Don't initialize `kmp_dep_info` instances in alloc regions (#131795)
Fixes #121289
Given the following MLIR, where a variable: `x`, is `private` for the
`omp.parallel` op and a `depend` for the `omp.task` op:
```mlir
omp.private {type = private} @_QFEx_private_i32 : i32
llvm.func @nested_task_with_deps() {
%0 = llvm.mlir.constant(1 : i64) : i64
%1 = llvm.alloca %0 x i32 {bindc_name = "x"} : (i64) -> !llvm.ptr
omp.parallel private(@_QFEx_private_i32 %1 -> %arg0 : !llvm.ptr) {
omp.task depend(taskdependout -> %arg0 : !llvm.ptr) {
omp.terminator
}
omp.terminator
}
llvm.return
}
```
Before the fix proposed by this PR, the IR builder would emit the
allocation and the initialzation logic for the task's depedency info
struct in the parent function's alloc region:
```llvm
define void @nested_task_with_deps() {
....
%.dep.arr.addr = alloca [1 x %struct.kmp_dep_info], align 8
%2 = getelementptr inbounds [1 x %struct.kmp_dep_info], ptr %.dep.arr.addr, i64 0, i64 0
%3 = getelementptr inbounds nuw %struct.kmp_dep_info, ptr %2, i32 0, i32 0
%4 = ptrtoint ptr %omp.private.alloc to i64
store i64 %4, ptr %3, align 4
....
br label %entry
omp.par.entry: ; preds = %entry
....
%omp.private.alloc = alloca i32, align 4
```
Note the following:
- The private value `x` is alloced where it should be in the parallel
op's entry region,
- howerver, since the privae value is also a depedency of the task and
since allocation and initialzation of the task depedency info struct
both happen in the alloc region,
- this results in the private value being referenced before it is
actually defined.
This PR fixes the issue by only allocating the task depedency info in
the alloc region while initialzation happens in the current IP of the
function with the rest of the logic that depends on it.
Commit: e737b846b4a34940b626c2a1119779caaa430460
https://github.com/llvm/llvm-project/commit/e737b846b4a34940b626c2a1119779caaa430460
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir
Log Message:
-----------
[flang][OpenMP] Translate OpenMP scopes when compiling for target device (#130078)
If a `target` directive is nested in a host OpenMP directive (e.g.
parallel, task, or a worksharing loop), flang currently crashes if the
target directive-related MLIR ops (e.g. `omp.map.bounds` and
`omp.map.info` depends on SSA values defined inside the parent host
OpenMP directives/ops.
This PR tries to solve this problem by treating these parent OpenMP ops
as "SSA scopes". Whenever we are translating for the device, instead of
completely translating host ops, we just tranlate their MLIR ops as pure
SSA values.
Commit: 8249492374b79793fe612da9d20aaa7e94832f91
https://github.com/llvm/llvm-project/commit/8249492374b79793fe612da9d20aaa7e94832f91
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
Log Message:
-----------
llvm-reduce: Remove redundant casts to InvokeInst
Commit: f304fd0d5c79024954f198a4714df6957cff5eef
https://github.com/llvm/llvm-project/commit/f304fd0d5c79024954f198a4714df6957cff5eef
Author: Matthias Springer <me at m-sp.org>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor][NFC] Remove dead code `tensor.extract_slice` canonicalization pattern (#131903)
Folding a cast into an `extract_slice` does not change the result type.
Commit: b907920058001ecb94fdd6939343fab5b786d96b
https://github.com/llvm/llvm-project/commit/b907920058001ecb94fdd6939343fab5b786d96b
Author: Shoreshen <372660931 at qq.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
Log Message:
-----------
[AMDGPU] auto-generate file check line for amdgcn.bitcast.ll (#131955)
Replace check lines by auto-generated
Commit: a1c8dda205aa4a7f1c861c620793cdd2e60f2131
https://github.com/llvm/llvm-project/commit/a1c8dda205aa4a7f1c861c620793cdd2e60f2131
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
Log Message:
-----------
[RISCV] Add attribute vscale_range(2,1024) to the tests for removing zero_extend on RV64. NFC (#131973)
The attribute `vscale_range(2,1024)` is added to each function by
default when the V extension is enabled,
so that the zero_extend for the i32 %evl to i64 on RV64 would be removed
usually.
Commit: 8a53324aa5c98787fe2334180a26b426f793d139
https://github.com/llvm/llvm-project/commit/8a53324aa5c98787fe2334180a26b426f793d139
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
A llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
Log Message:
-----------
[AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR mode (#130037)
In dynamic VGPR mode, Waves must deallocate all VGPRs before exiting. If
the shader program does not do this, hardware inserts `S_ALLOC_VGPR 0`
before S_ENDPGM, but this may incur some performance cost. Therefore
it's better if the compiler proactively generates that instruction.
This patch extends `si-insert-waitcnts` to deallocate the VGPRs via a
`S_ALLOC_VGPR 0` before any `S_ENDPGM` when in dynamic VGPR mode.
Commit: e9988c36ed788b2d1ce00b028bed51169bd8b02c
https://github.com/llvm/llvm-project/commit/e9988c36ed788b2d1ce00b028bed51169bd8b02c
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CodeGenCXX/derived-to-base.cpp
A clang/test/SemaCXX/derived-to-base-propagate-qualifiers.cpp
Log Message:
-----------
[clang][Sema] Propagate qualifiers during derived-to-base conversion
When accessing a field member through a derived-to-base conversion,
ensure qualifiers are propagated to the base class subobject.
Fixes: https://github.com/llvm/llvm-project/issues/127683.
Commit: 614d8557dcd41aae31bd50e93fed3487f235ef11
https://github.com/llvm/llvm-project/commit/614d8557dcd41aae31bd50e93fed3487f235ef11
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/include/clang/Driver/OffloadBundler.h
M clang/lib/Driver/OffloadBundler.cpp
Log Message:
-----------
[OffloadBundler] Expose function to parse compressed bundle headers (#130284)
In COMGR we hash the header of compressed bundles. For this we take the
first bytes of the buffer (according to the maximum header size) and
hash them.
To have a more stable API, and to be able to pick only the hash field (which is
the only one we are actually interested in) of the header, we propose
a version independent header version that is common to all versions.
Commit: 74f5a028cb612e7e9bcf75d8ceb1a0a9d20fdb80
https://github.com/llvm/llvm-project/commit/74f5a028cb612e7e9bcf75d8ceb1a0a9d20fdb80
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
A llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
Log Message:
-----------
Reapply "[AArch64][SVE] Improve fixed-length addressing modes. (#129732)" (#130625)
The original patch from #129732 exposed a bug in `getMemVTFromNode`, which was returning incorrect types for fixed length vectors.
Commit: 415dd383e4066717178870f1927f542a3d96621a
https://github.com/llvm/llvm-project/commit/415dd383e4066717178870f1927f542a3d96621a
Author: liulin92 <lindanliulin at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
Log Message:
-----------
[RISCV][MC] Correct the register state update for auipc (#130897)
AUIPC is a 20-bits value which is used to form 32-bits offset thus it
should be a int32 value, then signed-extend to int64.
Commit: 7dbcdd578cd4d37b1f4094dbd17556be6382f1cc
https://github.com/llvm/llvm-project/commit/7dbcdd578cd4d37b1f4094dbd17556be6382f1cc
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M lldb/include/lldb/Core/Telemetry.h
M lldb/source/Core/Telemetry.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
Log Message:
-----------
Revert "[LLDB][Telemetry]Define TargetInfo for collecting data about a target (#127834)"
This reverts commit 04e39ce3fddaaec41d9c7babcca55133d7e49969 due to test
breakage.
Commit: b8271ec8b3a19e4b7ba0a6c10af927e601380be8
https://github.com/llvm/llvm-project/commit/b8271ec8b3a19e4b7ba0a6c10af927e601380be8
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
Log Message:
-----------
[flang] accept character type in fir::changeTypeShape (#131892)
There is no reason for character element type to be forbidden in this
helper.
The assert was firing in character pointer assignment in FORALL after
#130772 added a usage of this helper.
Commit: f3f7f08ecaf0889b16bbe11fd6c9d38586979b1e
https://github.com/llvm/llvm-project/commit/f3f7f08ecaf0889b16bbe11fd6c9d38586979b1e
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Fix Wsign-compare warning (NFC) (#131948)
llvm-project/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:4805:57:
warning: comparison of integer expressions of different signedness:
‘int’ and ‘std::size_t’ {aka ‘long unsigned int’} [-Wsign-compare]
[](const auto &P) { return P.value() % 2 != P.index() % 2; }))
~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
Commit: 72240fae4a2c305432b30998cb1d43bebefcad8a
https://github.com/llvm/llvm-project/commit/72240fae4a2c305432b30998cb1d43bebefcad8a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/select-codesize.ll
R llvm/test/Analysis/CostModel/X86/select-latency.ll
R llvm/test/Analysis/CostModel/X86/select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/select.ll
Log Message:
-----------
[CostModel][X86] merge select costs tests using -cost-kind=all (#131865)
Commit: 0f2fb2b5c5c5052cb18a4b2c3330d43286f95ad2
https://github.com/llvm/llvm-project/commit/0f2fb2b5c5c5052cb18a4b2c3330d43286f95ad2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/mul-codesize.ll
R llvm/test/Analysis/CostModel/X86/mul-latency.ll
R llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul.ll
M llvm/test/Analysis/CostModel/X86/mul32.ll
M llvm/test/Analysis/CostModel/X86/mul64.ll
Log Message:
-----------
[CostModel][X86] merge integer multiply costs tests using -cost-kind=all (#131864)
Commit: 1f844952558b041ff1b4c27eed7b81c15841ee84
https://github.com/llvm/llvm-project/commit/1f844952558b041ff1b4c27eed7b81c15841ee84
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
Log Message:
-----------
[AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (#130047)
In dynamic VGPR mode, we can allocate up to 8 blocks of either 16 or 32
VGPRs (based on a chip-wide setting which we can model with a Subtarget
feature). Update some of the subtarget helpers to reflect this.
In particular:
- getVGPRAllocGranule is set to the block size
- getAddresableNumVGPR will limit itself to 8 * size of a block
We also try to be more careful about how many VGPR blocks we allocate.
Therefore, when deciding if we should revert scheduling after a given
stage, we check that we haven't increased the number of VGPR blocks that
need to be allocated.
---------
Co-authored-by: Jannik Silvanus <jannik.silvanus at amd.com>
Commit: 434ac4612f2b43a5b7f1a8e3b5310e8d129360e6
https://github.com/llvm/llvm-project/commit/434ac4612f2b43a5b7f1a8e3b5310e8d129360e6
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
A clang/test/Modules/diag-undefined-template.cpp
Log Message:
-----------
Improve the -Wundefined-func-template diagnostic note for invisible template functions (#129031)
See discussion in https://github.com/llvm/llvm-project/issues/125071.
Makes the note clearer for the unreachable case:
Before:
```
./hoge.h:5:12: warning: instantiation of function 'x<int>' required here, but no definition is available [-Wundefined-func-template]
5 | void f() { x<int>(); }
| ^
./shared_ptr2.h:4:6: note: forward declaration of template entity is here
4 | void x() { T t; (void)t; }
| ^
./hoge.h:5:12: note: add an explicit instantiation declaration to suppress this warning if 'x<int>' is explicitly instantiated in another translation unit
5 | void f() { x<int>(); }
|
```
After:
```
./hoge.h:5:12: warning: instantiation of function 'x<int>' required here, but no definition is available [-Wundefined-func-template]
5 | void f() { x<int>(); }
| ^
./shared_ptr2.h:4:6: note: declaration of template entity is unreachable here
4 | void x() { T t; (void)t; }
| ^
1 warning generated.
```
Commit: 9762b8e1757601a719d926f7df77c207617adfdd
https://github.com/llvm/llvm-project/commit/9762b8e1757601a719d926f7df77c207617adfdd
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
Log Message:
-----------
[NFC][analyzer] Document the VirtualCall checkers (#131861)
This commit documents `cplusplus.PureVirtualCall` (which was previously
completely undocumented) and improves the documentation of
`optin.cplusplus.VirtualCall` (which was very barebones).
Note that in this documentation I do not mention the checker options of
`optin.cplusplus.VirtualCall`, because `ShowFixIts` is apparently in an
unfinished alpha state (since 2019 when it was added by commit
6cee434ed10ead6b7416ca5ee9592b2b207eeb0f) and `PureOnly` is a deprecated
option that I'm going to remove very soon.
Commit: 61b0bf5e01589182c2447e9a978c34a4d7cef5f3
https://github.com/llvm/llvm-project/commit/61b0bf5e01589182c2447e9a978c34a4d7cef5f3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
R llvm/test/Analysis/CostModel/X86/fshl-latency.ll
R llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
R llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
R llvm/test/Analysis/CostModel/X86/fshr-latency.ll
R llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
Log Message:
-----------
[CostModel][X86] merge funnel shifts costs tests using -cost-kind=all (#131867)
Commit: 96ad7ef77655362dd818fda4685c14776fe5dbf3
https://github.com/llvm/llvm-project/commit/96ad7ef77655362dd818fda4685c14776fe5dbf3
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
Log Message:
-----------
[NFC][analyzer] Correct example code in VirtualCall docs (#131992)
Oops, I noticed these just after merging my commit
9762b8e1757601a719d926f7df77c207617adfdd.
Commit: 7cd9b3fcec87b02bdbc9308dbff9afa0f55e96d5
https://github.com/llvm/llvm-project/commit/7cd9b3fcec87b02bdbc9308dbff9afa0f55e96d5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/trunc-codesize.ll
R llvm/test/Analysis/CostModel/X86/trunc-latency.ll
R llvm/test/Analysis/CostModel/X86/trunc-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/trunc.ll
Log Message:
-----------
[CostModel][X86] merge truncation costs tests using -cost-kind=all (#131872)
Commit: 841d6c45f36084e1023803647b8c48158911e475
https://github.com/llvm/llvm-project/commit/841d6c45f36084e1023803647b8c48158911e475
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/fcmp-codesize.ll
R llvm/test/Analysis/CostModel/X86/fcmp-latency.ll
R llvm/test/Analysis/CostModel/X86/fcmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fcmp.ll
Log Message:
-----------
[CostModel][X86] merge fp comparison costs tests using -cost-kind=all (#131874)
Commit: e9daafdd5ec76420abe8666a86d19ba330567107
https://github.com/llvm/llvm-project/commit/e9daafdd5ec76420abe8666a86d19ba330567107
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/icmp-codesize.ll
R llvm/test/Analysis/CostModel/X86/icmp-latency.ll
R llvm/test/Analysis/CostModel/X86/icmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/icmp.ll
M llvm/test/Analysis/CostModel/X86/icmp0.ll
Log Message:
-----------
[CostModel][X86] merge integer comparison costs tests using -cost-kind=all (#131875)
Commit: 6ca1424fc1db255627f27eb6a50c7a837e3fecb3
https://github.com/llvm/llvm-project/commit/6ca1424fc1db255627f27eb6a50c7a837e3fecb3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/fmaxnum-codesize.ll
R llvm/test/Analysis/CostModel/X86/fmaxnum-latency.ll
R llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll
M llvm/test/Analysis/CostModel/X86/fmaxnum.ll
R llvm/test/Analysis/CostModel/X86/fminnum-codesize.ll
R llvm/test/Analysis/CostModel/X86/fminnum-latency.ll
R llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll
M llvm/test/Analysis/CostModel/X86/fminnum.ll
Log Message:
-----------
[CostModel][X86] merge fmaxnum/fminnum costs tests using -cost-kind=all (#131922)
Commit: 75ab43b70eef125dbdf1586143fad88a2a61170e
https://github.com/llvm/llvm-project/commit/75ab43b70eef125dbdf1586143fad88a2a61170e
Author: Andrey Timonin <timonina1909 at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc][NFC] Eliminate the extra newline printout during emitc.switch emission (#129257)
Before the output was:
```c++
void emitc_switch_ptrdiff_t() {
ptrdiff_t v1 = 1;
switch (v1) {
...
}
return;
}
```
After:
```c++
void emitc_switch_ptrdiff_t() {
ptrdiff_t v1 = 1;
switch (v1) {
...
}
return;
}
```
Commit: e7c6e3557b372afe6e78c025addfec276a10b49d
https://github.com/llvm/llvm-project/commit/e7c6e3557b372afe6e78c025addfec276a10b49d
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/threadprivate-common-block-pointer.f90
Log Message:
-----------
[flang][OpenMP] Fix threadprivate pointer variable in common block (#131888)
Fixes #112538
The problem was that the host associated symbol for the threadprivate
variable doesn't have all of the symbol attributes (e.g. POINTER). This
caused the lowering code to generate the wrong type, eventually hitting
an assertion.
Commit: 1d7c4609445cb0a8330ee06b836d3c873d7f12bb
https://github.com/llvm/llvm-project/commit/1d7c4609445cb0a8330ee06b836d3c873d7f12bb
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
Log Message:
-----------
[RISCV] Set isTrap for EBREAK and {C_,}UNIMP (#131636)
This is done for completeness. The property isn't used in upstream
llvm/, although it is queried in BOLT in MCPlusBuilder.cpp.
Commit: 541ab52ca9b0a3163b42665bf469a4499a7aea44
https://github.com/llvm/llvm-project/commit/541ab52ca9b0a3163b42665bf469a4499a7aea44
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/test/Modules/eagerly-load-cxx-named-modules.cppm
Log Message:
-----------
[clang] Add a missing space to the -Weager-load-cxx-named-modules diagnostic message. (#131987)
Commit: ee8a759bfb4772dea7459f4ecbd83bc2be5ee68b
https://github.com/llvm/llvm-project/commit/ee8a759bfb4772dea7459f4ecbd83bc2be5ee68b
Author: swatheesh-mcw <swatheesh.muralidharan at multicorewareinc.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
A flang/test/Lower/OpenMP/Todo/inteorp-construct.f90
A flang/test/Parser/OpenMP/interop-construct.f90
A flang/test/Semantics/OpenMP/interop-construct.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][openmp] Adds Parser and Semantic Support for Interop Construct, and Init and Use Clauses. (#120584)
Adds Parser and Semantic Support for the below construct and clauses:
- Interop Construct
- Init Clause
- Use Clause
Note:
The other clauses supported by Interop Construct such as Destroy, Use,
Depend and Device are added already.
Commit: 6dba5f659567af21a01224845077a269380d8e3a
https://github.com/llvm/llvm-project/commit/6dba5f659567af21a01224845077a269380d8e3a
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI] Align optional FMFs in getExtendedReductionCost() to getArithmeticReductionCost(). (#131968)
In the implementation of the getExtendedReductionCost(), it ofter calls
getArithmeticReductionCost() with FMFs. But we shouldn't call
getArithmeticReductionCost() with FMFs for non-floating-point reductions
which will return the wrong cost.
This patch makes FMFs in getExtendedReductionCost() optional and align
to the getArithmeticReductionCost(). So the TTI will return the correct
cost for non-FP extended-reductions query without FMFs.
This patch is not quite NFC but it's hard to test from the CostModel
side.
Split from #113903.
Commit: b7eb01b3a15d59be58319705c916ddf6859d0aab
https://github.com/llvm/llvm-project/commit/b7eb01b3a15d59be58319705c916ddf6859d0aab
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[NFC][OpenMP][MLIR] Refactor code related to collecting privatizer info into a shared util (#131582)
Moves code needed to collect info about delayed privatizers into a
shared util instread of repeating the same patter across all relevant
constructs.
Commit: 96b112fb613e216a198ae2e956a367742c838eed
https://github.com/llvm/llvm-project/commit/96b112fb613e216a198ae2e956a367742c838eed
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
R flang/test/Lower/OpenMP/Todo/inteorp-construct.f90
R flang/test/Parser/OpenMP/interop-construct.f90
R flang/test/Semantics/OpenMP/interop-construct.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
Revert "[flang][openmp] Adds Parser and Semantic Support for Interop Construct, and Init and Use Clauses." (#132005)
Reverts llvm/llvm-project#120584
Reverting due to CI failure
https://lab.llvm.org/buildbot/#/builders/157/builds/22946
Commit: 6db2594c48b0aa5b13f5ac1664bcc42e836163c9
https://github.com/llvm/llvm-project/commit/6db2594c48b0aa5b13f5ac1664bcc42e836163c9
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-pattern.ll
Log Message:
-----------
[PreISelIntrinsicLowering] Zext/trunc count parameter as necessary for memset_pattern16 emission (#129239)
This patch cleans up the handling of the count parameter in general,
though was initially motivated by a compiler crash upon a memset.pattern
with a narrow count causing a compiler crash due to different types for
CreateMul when converting the count to the number of bytes.
The logic used to name globals means there is some minor renaming churn
in the output to
test/Transforms/PreISelIntrinsicLowering/X86/memset-pattern.ll
irrelevant to the newly added tests (that would crash before).
Commit: 571e4de02ee527ef6d0399008fb57440e51c5d22
https://github.com/llvm/llvm-project/commit/571e4de02ee527ef6d0399008fb57440e51c5d22
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp
M lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/CompactUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
Log Message:
-----------
[lldb] Use UnwindPlan::Row as values (#131150)
In most places, the rows are copied anyway (because they are generated
by cumulating modifications) immediately after adding them to the unwind
plans. In others, they can be moved into the unwind plan. This lets us
remove some backflip copies and make `const UnwindPlan` actually mean
something.
I've split this patch into two (and temporarily left both APIs) as this
patch was getting a bit big. This patch covers all the interesting
cases. Part two all about converting "architecture default" unwind plans
from ABI and InstructionEmulation plugins.
Commit: 4686b8a6630a9e6c9a3736d624ce94a5030ce10c
https://github.com/llvm/llvm-project/commit/4686b8a6630a9e6c9a3736d624ce94a5030ce10c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
Log Message:
-----------
[CostModel][X86] merge masked intrinsics costs tests using -cost-kind=all (#131999)
Commit: 945ce9642b5d02386abe2f58b6966ca9efc5abf1
https://github.com/llvm/llvm-project/commit/945ce9642b5d02386abe2f58b6966ca9efc5abf1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/Analysis/CostModel/X86/reduce-add.ll
M llvm/test/Analysis/CostModel/X86/reduce-and.ll
M llvm/test/Analysis/CostModel/X86/reduce-fadd.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmax.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmin.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmul.ll
M llvm/test/Analysis/CostModel/X86/reduce-mul.ll
M llvm/test/Analysis/CostModel/X86/reduce-or.ll
M llvm/test/Analysis/CostModel/X86/reduce-smax.ll
M llvm/test/Analysis/CostModel/X86/reduce-smin.ll
M llvm/test/Analysis/CostModel/X86/reduce-umax.ll
M llvm/test/Analysis/CostModel/X86/reduce-umin.ll
M llvm/test/Analysis/CostModel/X86/reduce-xor.ll
M llvm/test/Analysis/CostModel/X86/reduction.ll
Log Message:
-----------
[CostModel][X86] check all reduction cost kinds using -cost-kind=all (#132000)
Commit: 5b6b4fdb4b07e1d0d9a647f40a30d47f26178e09
https://github.com/llvm/llvm-project/commit/5b6b4fdb4b07e1d0d9a647f40a30d47f26178e09
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
DAG: Fix promote of half freeze (#131844)
Commit: e0db41615bd43c874d3b27ea5fe40a5940161f74
https://github.com/llvm/llvm-project/commit/e0db41615bd43c874d3b27ea5fe40a5940161f74
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Fix initializing array struct fields from an APValue (#131983)
We need to recurse once more here and move the array case into the
bigger if chain.
Commit: 449cdfacc07bd365d49a637196ce8f8067cf845c
https://github.com/llvm/llvm-project/commit/449cdfacc07bd365d49a637196ce8f8067cf845c
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang-tools-extra/clangd/Preamble.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/Lexer.cpp
M clang/test/C/C2y/n3411.c
A clang/test/CXX/drs/cwg787.cpp
R clang/test/Lexer/newline-eof-c++98-compat.cpp
M clang/test/Lexer/newline-eof.c
Log Message:
-----------
Suppress pedantic diagnostic for a file not ending in EOL (#131794)
WG14 added N3411 to the list of papers which apply to older versions of
C in C2y, and WG21 adopted CWG787 as a Defect Report in C++11. So we no
longer should be issuing a pedantic diagnostic about a file which does
not end with a newline character.
We do, however, continue to support -Wnewline-eof as an opt-in
diagnostic.
Commit: 6c773a87013cf82b68ba9be4672e3908a9ab6010
https://github.com/llvm/llvm-project/commit/6c773a87013cf82b68ba9be4672e3908a9ab6010
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
Log Message:
-----------
[LLVM][SVE] Implement isel for bfloat fptoi and itofp operations. (#129713)
NOTE: This PR only considers scalable vectors because SVE VLS does not
support bfloat (see useSVEForFixedLengthVectorVT()).
Commit: 3adf2b00aef80fa313faf668a50eae4cf41334a5
https://github.com/llvm/llvm-project/commit/3adf2b00aef80fa313faf668a50eae4cf41334a5
Author: Aleksandr Korepanov <alexander.korepanov at jetbrains.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/unittests/DebugInfo/PDB/PDBVariantTest.cpp
Log Message:
-----------
[LLVM][PDB][Test] Fix the build (#131984)
Hello! Sorry, it seems I broke the build in
https://github.com/llvm/llvm-project/pull/131598
Build:
https://lab.llvm.org/buildbot/#/builders/145/builds/5745
This is a compilation fix, please take a look.
Commit: 3c554deaaaa9aaa4f1aebc0d19f56424a32fe5e3
https://github.com/llvm/llvm-project/commit/3c554deaaaa9aaa4f1aebc0d19f56424a32fe5e3
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
Log Message:
-----------
[LV] Add reg-usage test with values only used by llvm.assume.
Add test checking we are not counting registers that are only used by
ephemeral users, like llvm.assume.
Commit: 4ddc8df6ca1c9c1a1f03f03baefba5d1f6e2e78b
https://github.com/llvm/llvm-project/commit/4ddc8df6ca1c9c1a1f03f03baefba5d1f6e2e78b
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
A llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
Log Message:
-----------
[CostModel][ARM]Adjust cost of muls in (U/S)MLAL and patterns (#122713)
PR #117350 made changes to the SLP vectorizer which introduced a
regression on some ARM benchmarks. Investigation narrowed it down to
suboptimal codegen for benchmarks that previously only used scalar (U/S)MLAL
instructions. The linked change meant the SLPVectorizer thought that
these could be vectorized. This change makes the cost of muls in
(U/S)MLAL patterns slightly cheaper to make sure scalar instructions are
preferred in these cases over SLP vectorization on targets supporting DSP
Commit: 861efd4b3f93d30d353f0a6eea249fbdac1778a0
https://github.com/llvm/llvm-project/commit/861efd4b3f93d30d353f0a6eea249fbdac1778a0
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M lldb/test/API/functionalities/reverse-execution/TestReverseContinueBreakpoints.py
M lldb/test/API/functionalities/reverse-execution/TestReverseContinueWatchpoints.py
Log Message:
-----------
[lldb] Skip reverse continue tests on x86_64-darwin
Tests are failing because some registers (at least `ds`) are unreadable.
Commit: 72c3c30452d340d1a90cd3e7efe685ee188003c7
https://github.com/llvm/llvm-project/commit/72c3c30452d340d1a90cd3e7efe685ee188003c7
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
A llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Log Message:
-----------
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
The CWSR trap handler needs to save and restore the VGPRs. When dynamic
VGPRs are in use, the fixed function hardware will only allocate enough
space for one VGPR block. The rest will have to be stored in scratch, at
offset 0.
This patch allocates the necessary space by:
- generating a prologue that checks at runtime if we're on a compute
queue (since CWSR only works on compute queues); for this we will have
to check the ME_ID bits of the ID_HW_ID2 register - if that is non-zero,
we can assume we're on a compute queue and initialize the SP and FP with
enough room for the dynamic VGPRs
- forcing all compute entry functions to use a FP so they can access
their locals/spills correctly (this isn't ideal but it's the quickest to
implement)
Note that at the moment we allocate enough space for the theoretical
maximum number of VGPRs that can be allocated dynamically (for blocks of
16 registers, this will be 128, of which we subtract the first 16, which
are already allocated by the fixed function hardware). Future patches
may decide to allocate less if they can prove the shader never allocates
that many blocks.
Also note that this should not affect any reported stack sizes (e.g. PAL
backend_stack_size etc).
Commit: 3eddb992d08b30832d2cc0908483f10fe133935a
https://github.com/llvm/llvm-project/commit/3eddb992d08b30832d2cc0908483f10fe133935a
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
A llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
Log Message:
-----------
[AMDGPU] Fix a crash by skipping DBG instrs at start of sched region (#131167)
Fixes SWDEV-514946
Commit: 7e3fe884ac5ffd2a32e8682459146494086ecc0a
https://github.com/llvm/llvm-project/commit/7e3fe884ac5ffd2a32e8682459146494086ecc0a
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilege.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehi.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehs.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilele.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilelo.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilels.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilelt.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilerw.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilewr.mir
Log Message:
-----------
[LLVM] Regenerate CHECK lines for CodeGen/AArch64/sve-ptest-removal-*.mir
Commit: 3f4b2f12a1e3e87e4bfb86937cc1ccdd4d38dcf5
https://github.com/llvm/llvm-project/commit/3f4b2f12a1e3e87e4bfb86937cc1ccdd4d38dcf5
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
A llvm/test/CodeGen/AArch64/complex-deinterleaving-unrolled-cdot.ll
Log Message:
-----------
[llvm] Fix crash when complex deinterleaving operates on an unrolled loop (#129735)
When attempting to perform complex deinterleaving on an unrolled loop
containing a reduction, the complex deinterleaving pass would fail to
accommodate the wider types when accumulating the unrolled paths.
Instead of trying to alter the incoming IR to fit expectations, the pass
should instead decide against processing any reduction that results in a
non-complex or non-vector value.
Commit: 29925b7044517bcd1b3f76333a598092427c3636
https://github.com/llvm/llvm-project/commit/29925b7044517bcd1b3f76333a598092427c3636
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Log Message:
-----------
[NFC][CostModel][ARM] Remove redundant lambda capture (#132018)
Buildbot failures were caused by PR #122713. This was due to unused captures in a lambda function.
Commit: 0aba8334f92b98cb2bf791565179e8dd63dce125
https://github.com/llvm/llvm-project/commit/0aba8334f92b98cb2bf791565179e8dd63dce125
Author: Nathan Gauër <brioche at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
A llvm/test/CodeGen/SPIRV/pointers/load-struct.ll
Log Message:
-----------
[SPIR-V] Handle struct member loading from ptrcast (#130089)
Adds support for loading the first element of an aggregate from a GEP
instruction & load to the member type.
Commit: 9654df3f5e8f898341717ac25097dba6f667c356
https://github.com/llvm/llvm-project/commit/9654df3f5e8f898341717ac25097dba6f667c356
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/StringSet.h
M llvm/unittests/ADT/StringSetTest.cpp
Log Message:
-----------
[ADT] Add StringSet::insert_range (#131957)
This pach adds StringSet::insert_range for consistency with
DenseSet::insert_range and std::set::insert_range from C++23.
In the unit test, I'm using contains instead of
testing::UnorderedElementsAre because the latter doesn't seem to work
with char *.
Commit: c3e334fc0d9dc12b25cde5839d993f70f56e5e76
https://github.com/llvm/llvm-project/commit/c3e334fc0d9dc12b25cde5839d993f70f56e5e76
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
Log Message:
-----------
[AMDGPU] Avoid repeated hash lookups (NFC) (#131958)
Commit: 099a11f4ab02d13fba6e5c36fdb89881075b6216
https://github.com/llvm/llvm-project/commit/099a11f4ab02d13fba6e5c36fdb89881075b6216
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#131959)
Commit: f97a852d69bd0434776e44136013dfb045e253ef
https://github.com/llvm/llvm-project/commit/f97a852d69bd0434776e44136013dfb045e253ef
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/IPO/IROutliner.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#131960)
Commit: fc278e406ec0204437e26f087a5a71d74727924e
https://github.com/llvm/llvm-project/commit/fc278e406ec0204437e26f087a5a71d74727924e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
[Scalar] Avoid repeated hash lookups (NFC) (#131961)
Commit: 9705010b5e1fc878a9107d844dcb641499d8c73f
https://github.com/llvm/llvm-project/commit/9705010b5e1fc878a9107d844dcb641499d8c73f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[Vectorize] Avoid repeated hash lookups (NFC) (#131962)
Commit: 364e60b6e41d49bc08be21cc279bba57ddabf679
https://github.com/llvm/llvm-project/commit/364e60b6e41d49bc08be21cc279bba57ddabf679
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
Log Message:
-----------
[X86] Avoid repeated hash lookups (NFC) (#131963)
Commit: 0cb9c5045b556c668e6d7b47f6a90032d2aa0f21
https://github.com/llvm/llvm-project/commit/0cb9c5045b556c668e6d7b47f6a90032d2aa0f21
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/test/Analysis/CostModel/X86/fptosi.ll
M llvm/test/Analysis/CostModel/X86/fptoui.ll
M llvm/test/Analysis/CostModel/X86/sitofp.ll
M llvm/test/Analysis/CostModel/X86/uitofp.ll
Log Message:
-----------
[CostModel][X86] check fp<->int conversion cost kinds using -cost-kind=all
Commit: baef6fadbf0e4ddac33c6a8a6275208435f52965
https://github.com/llvm/llvm-project/commit/baef6fadbf0e4ddac33c6a8a6275208435f52965
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/ParsedAttr.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/ParsedAttr.cpp
M clang/test/Parser/parser_overflow.c
Log Message:
-----------
[Clang] Increase the default expression nesting limit (#132021)
This iterates on #104717 (which we had to revert)
In a bid to increase our chances of success, we try to avoid blowing up
the stack by
- Using `runWithSufficientStackSpace` in ParseCompoundStatement
- Reducing the size of `StmtVector` a bit
- Reducing the size of `DeclsInGroup` a bit
- Removing a few `ParsedAttributes` from the stacks in places where they
are not strictly necessary. `ParsedAttributes` is a _huge_ object
On a 64 bits system, the following stack size reductions are observed
```
ParseStatementOrDeclarationAfterAttributes: 344 -> 264
ParseStatementOrDeclaration: 520 -> 376
ParseCompoundStatementBody: 1080 -> 1016
ParseDeclaration: 264 -> 120
```
Fixes #94728
Commit: be0a3b223a10e0a3e588b1d6002581982968f0f4
https://github.com/llvm/llvm-project/commit/be0a3b223a10e0a3e588b1d6002581982968f0f4
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/Verifier.cpp
A llvm/test/Verifier/memset-pattern-unsized.ll
Log Message:
-----------
[IR] Allow llvm.experimental.memset.pattern to take any sized type as the pattern argument (#132026)
I initially thought starting with a more narrow definition and later
expanding would make more sense. But as pointed out in review for PR
#129220, this restriction is generating additional unnecessary work.
This patch alters the intrinsic to accept patterns of any type. Future
patches will update LoopIdiomRecognize and PreISelIntrinsicLowering to
take advantage of this. The verifier will complain if an unsized type is
used. I've additionally taken the opportunity to remove a comment from
the LangRef about some bit widths potentially not being supported by the
target. I don't think this is any more true than it is for arbitrary
width loads/stores which don't carry a similar warning that I can see.
A verifier check ensures that only sized types are used for the pattern.
Commit: ade22fc1d9616c95bd1aa4ea658a21ddb073b73c
https://github.com/llvm/llvm-project/commit/ade22fc1d9616c95bd1aa4ea658a21ddb073b73c
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/test/CodeGen/PowerPC/f128-conv.ll
M llvm/test/CodeGen/PowerPC/fp128-libcalls.ll
Log Message:
-----------
[PowerPC] Support conversion between f16 and f128 (#130158)
Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.
Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of: https://github.com/llvm/llvm-project/pull/97677
---------
Co-authored-by: esmeyi <esme.yi at ibm.com>
Commit: 20feca47c1e2fdd90f3f7007a492e4ec18c71c08
https://github.com/llvm/llvm-project/commit/20feca47c1e2fdd90f3f7007a492e4ec18c71c08
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/module/ieee_arithmetic.f90
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Allow ieee_arithmetic on the device (#131930)
- Allow ieee_arithmetic on the device
- Add ignore_tkr(d) to ieee_is_finite
Commit: 2d090287712a650734397ef4642c7888fe239281
https://github.com/llvm/llvm-project/commit/2d090287712a650734397ef4642c7888fe239281
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M libc/test/src/search/lsearch_test.cpp
Log Message:
-----------
[libc] Fix `size_t` and `unsigned long` mismatch on riscv32 in test. (#132028)
Fix regression:
https://github.com/llvm/llvm-project/pull/131431#issuecomment-2735029529
Commit: 67a01131a8d70fcd06c6bd9cea30a8a6262c8c94
https://github.com/llvm/llvm-project/commit/67a01131a8d70fcd06c6bd9cea30a8a6262c8c94
Author: Iris <0.0 at owo.li>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M libc/src/sched/linux/sched_getcpucount.cpp
Log Message:
-----------
[libc] Replace `__builtin_popcountl` with `cpp::popcount` in `sched_getcpucount` (#131952)
Closes #128781.
Commit: 38e8dff84ba1e2cf0260712d21dd429d74471d08
https://github.com/llvm/llvm-project/commit/38e8dff84ba1e2cf0260712d21dd429d74471d08
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/call.ll
Log Message:
-----------
[AA][BasicAA] Move more call logic to BasicAA (#131144)
Currently, the handling for calls is split between AA and BasicAA in an
awkward way. BasicAA does argument alias analysis for non-escaping
objects (but without considering MemoryEffects), while AA handles the
generic case using MemoryEffects. However, fundamentally, both of these
are really trying to do the same thing.
The new merged logic first tries to remove the OtherMR component of the
memory effects, which includes accesses to escaped memory. If a
function-local object does not escape, OtherMR can be set to NoModRef.
Then we perform the argument scan in basically the same way as AA
previously did. However, we also need to look at the operand bundles. To
support that, I've adjusted getArgModRefInfo to accept operand bundle
arguments.
Commit: 4322d03e4acce4eb0ba7c274d38015061e34a9c1
https://github.com/llvm/llvm-project/commit/4322d03e4acce4eb0ba7c274d38015061e34a9c1
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M lldb/bindings/headers.swig
Log Message:
-----------
[lldb] Avoid having to list all the headers in headers.swig (#131934)
When adding SBLock, I realized you always have to add a new header in
two places: LLDB.h and headers.swig.
I can't think of a reason the latter can't use the umbrella header and
avoid the duplication.
Commit: b3d280b887780c04e89dc0214ac800d37bbb4009
https://github.com/llvm/llvm-project/commit/b3d280b887780c04e89dc0214ac800d37bbb4009
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/gfni-lzcnt.ll
M llvm/test/CodeGen/X86/vector-lzcnt-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] fold AND(X,SEXT(SETCC())) -> SELECT(SETCC(),X,0) to support AVX512 predicated {k}{z} masks (#131788)
We already do this for the ANDNP(SEXT(SETCC()),X) equivalent pattern.
Fixes #109272
Commit: 2b8f887915020431112c35397368edd34b313f9a
https://github.com/llvm/llvm-project/commit/2b8f887915020431112c35397368edd34b313f9a
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/CMakeLists.txt
A mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h
A mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
A mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrTypes.h
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/test/Dialect/Ptr/layout.mlir
M mlir/test/Dialect/Ptr/types.mlir
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
M mlir/test/lib/Dialect/Test/TestAttributes.h
Log Message:
-----------
[mlir][Ptr] Add the `MemorySpaceAttrInterface` interface and dependencies. (#86870)
This patch introduces the `MemorySpaceAttrInterface` interface. This
interface is responsible for handling the semantics of `ptr` operations.
For example, this interface can be used to create read-only memory
spaces, making any other operation other than a load a verification
error, see `TestConstMemorySpaceAttr` for a possible implementation of
this concept.
This patch also introduces Enum dependencies `AtomicOrdering`, and
`AtomicBinOp`, both enumerations are clones of the Enums with the same
name in the LLVM Dialect.
Also, see:
- [[RFC] `ptr` dialect & modularizing ptr ops in the LLVM
dialect](https://discourse.llvm.org/t/rfc-ptr-dialect-modularizing-ptr-ops-in-the-llvm-dialect/75142)
for rationale.
- https://github.com/llvm/llvm-project/pull/73057 for a prototype
implementation of the full change.
**Note: Ignore the first commit, that's being reviewed in
https://github.com/llvm/llvm-project/pull/86860 .**
Commit: 3bba268013680d7bf86a3aedbf0e91930362bda1
https://github.com/llvm/llvm-project/commit/3bba268013680d7bf86a3aedbf0e91930362bda1
Author: Ash Dobrescu <ash.dobrescu at arm.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/computed-goto.s
A bolt/test/Inputs/indirect_goto.c
R bolt/test/X86/Inputs/indirect_goto.c
R bolt/test/X86/indirect-goto-pie.test
M bolt/test/X86/indirect-goto.test
A bolt/test/indirect-goto-relocs.test
Log Message:
-----------
[BOLT] Support computed goto and allow map addrs inside functions (#120267)
Create entry points for addresses referenced by dynamic relocations and
allow getNewFunctionOrDataAddress to map addrs inside functions. By
adding addresses referenced by dynamic relocations as entry points. This
patch fixes an issue where bolt fails on code using computing goto's.
This also fixes a mapping issue with the bugfix from this PR:
https://github.com/llvm/llvm-project/pull/117766.
Commit: f536f715800658567ba619ad8a2b361d4d715fe9
https://github.com/llvm/llvm-project/commit/f536f715800658567ba619ad8a2b361d4d715fe9
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Split RecurrenceDescriptor into RecurKind + FastMathFlags in LoopUtils. NFC (#132014)
Split off from #131300, this splits up RecurrenceDescriptor arguments so
that arbitrary recurrence kinds may be used down the line.
Commit: 22583d0cf6b8e9d64d7bf10f1a34fd051a5811bd
https://github.com/llvm/llvm-project/commit/22583d0cf6b8e9d64d7bf10f1a34fd051a5811bd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M .ci/compute-projects.sh
M .ci/generate-buildkite-pipeline-premerge
M .ci/metrics/metrics.py
M .ci/monolithic-linux.sh
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
M bolt/lib/Target/AArch64/AArch64MCSymbolizer.h
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
A bolt/test/AArch64/computed-goto.s
A bolt/test/AArch64/got-load-symbolization.s
M bolt/test/AArch64/test-indirect-branch.s
A bolt/test/Inputs/indirect_goto.c
R bolt/test/X86/Inputs/indirect_goto.c
R bolt/test/X86/indirect-goto-pie.test
M bolt/test/X86/indirect-goto.test
A bolt/test/indirect-goto-relocs.test
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/CapturingThisInMemberVariableCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/CapturingThisInMemberVariableCheck.h
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.cpp
M clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
M clang-tools-extra/clangd/Preamble.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/capturing-this-in-member-variable.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/capturing-this-in-member-variable.cpp
M clang/docs/ClangOffloadBundler.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/Statistics.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.h
M clang/include/clang/Analysis/ProgramPoint.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/OffloadBundler.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Lex/Lexer.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/ParsedAttr.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaCodeCompletion.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/clang/StaticAnalyzer/Core/BugReporter/BugType.h
M clang/include/clang/StaticAnalyzer/Core/Checker.h
M clang/include/clang/StaticAnalyzer/Core/CheckerManager.h
A clang/include/clang/StaticAnalyzer/Core/PathSensitive/EntryPointStats.h
M clang/include/clang/Support/Compiler.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
A clang/include/clang/Tooling/DependencyScanning/InProcessModuleCache.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/FrontendAction/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPUtility.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
A clang/lib/Headers/hlsl/hlsl_compat_overloads.h
M clang/lib/Headers/hlsl/hlsl_intrinsic_helpers.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/ParseStmtAsm.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/ParsedAttr.cpp
M clang/lib/Sema/SemaAccess.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/AnalyzerStatsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/DivZeroChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/UnixAPIChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
M clang/lib/StaticAnalyzer/Core/AnalyzerOptions.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/CMakeLists.txt
M clang/lib/StaticAnalyzer/Core/Checker.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
A clang/lib/StaticAnalyzer/Core/EntryPointStats.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/lib/StaticAnalyzer/Core/WorkList.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/lib/Tooling/DependencyScanning/CMakeLists.txt
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/lib/Tooling/DependencyScanning/InProcessModuleCache.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/ast-dump-comment-cbuffer.hlsl
M clang/test/AST/HLSL/cbuffer.hlsl
M clang/test/AST/HLSL/cbuffer_and_namespaces.hlsl
M clang/test/AST/HLSL/packoffset.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
M clang/test/AST/HLSL/resource_binding_attr.hlsl
M clang/test/Analysis/Checkers/WebKit/mock-system-header.h
M clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
M clang/test/Analysis/analyzer-config.c
A clang/test/Analysis/analyzer-stats/entry-point-stats.cpp
A clang/test/Analysis/csv2json.py
A clang/test/Analysis/fixed-address-notes.c
A clang/test/C/C2y/n3353.c
M clang/test/C/C2y/n3411.c
A clang/test/CIR/CodeGen/cast.cpp
M clang/test/CIR/CodeGen/unary-expr-or-type-trait.cpp
A clang/test/CIR/CodeGen/unary.cpp
A clang/test/CIR/IR/cast.cir
A clang/test/CIR/Lowering/cast.cir
A clang/test/CIR/Tools/cir-translate-triple.cir
A clang/test/CIR/Tools/has-triple-and-data-layout.cir
A clang/test/CIR/Tools/has-triple-no-data-layout.cir
A clang/test/CIR/Tools/invalid-translate-triple.cir
A clang/test/CIR/Tools/no-triple-has-data-layout.cir
A clang/test/CIR/Tools/no-triple-no-data-layout.cir
A clang/test/CIR/Tools/warn-default-triple.cir
M clang/test/CXX/drs/cwg14xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
A clang/test/CXX/drs/cwg787.cpp
A clang/test/ClangScanDeps/modules-in-stable-dirs.c
A clang/test/ClangScanDeps/prebuilt-modules-in-stable-dirs.c
A clang/test/CodeCompletion/if-const.cpp
M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
M clang/test/CodeGen/arm-mve-intrinsics/admin.c
A clang/test/CodeGen/cx-complex-range-real.c
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/fake-use-determinism.c
M clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
M clang/test/CodeGenCXX/builtins.cpp
M clang/test/CodeGenCXX/derived-to-base.cpp
A clang/test/CodeGenCXX/gnu-asm-constexpr.cpp
M clang/test/CodeGenCXX/mangle.cpp
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/CodeGenOpenCL/kernel-attributes.cl
M clang/test/Driver/apple-arm64-arch.c
M clang/test/Driver/clang-offload-bundler-asserts-on.c
M clang/test/Driver/clang-offload-bundler-standardize.c
M clang/test/Driver/clang-offload-bundler.c
M clang/test/Driver/compilation_database_multiarch.c
M clang/test/Driver/darwin-ld-platform-version-macos-requires-darwin.c
M clang/test/Driver/hip-link-bc-to-bc.hip
M clang/test/Driver/hip-link-bundle-archive.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/mtargetos-darwin.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-features.c
M clang/test/Driver/xros-driver-requires-darwin-host.c
M clang/test/Index/pch-from-libclang.c
R clang/test/Lexer/newline-eof-c++98-compat.cpp
M clang/test/Lexer/newline-eof.c
A clang/test/Modules/diag-undefined-template.cpp
M clang/test/Modules/eagerly-load-cxx-named-modules.cppm
M clang/test/Parser/asm.cpp
M clang/test/Parser/parser_overflow.c
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M clang/test/Sema/aarch64-sve-vector-exp-ops.c
M clang/test/Sema/aarch64-sve-vector-log-ops.c
M clang/test/Sema/aarch64-sve-vector-pow-ops.c
M clang/test/Sema/aarch64-sve-vector-trig-ops.c
M clang/test/Sema/builtins-elementwise-math.c
M clang/test/Sema/builtins-reduction-math.c
M clang/test/Sema/count-builtins.c
M clang/test/Sema/riscv-rvv-vector-exp-ops.c
M clang/test/Sema/riscv-rvv-vector-log-ops.c
M clang/test/Sema/riscv-rvv-vector-trig-ops.c
M clang/test/Sema/riscv-sve-vector-pow-ops.c
A clang/test/SemaCXX/builtin-structured-binding-size.cpp
M clang/test/SemaCXX/concept-crash-on-diagnostic.cpp
M clang/test/SemaCXX/cxx2c-enum-compare.cpp
A clang/test/SemaCXX/derived-to-base-propagate-qualifiers.cpp
A clang/test/SemaCXX/gnu-asm-constexpr.cpp
M clang/test/SemaCXX/unique_object_duplication.h
A clang/test/SemaCXX/unnecessary-virtual-specifier.cpp
A clang/test/SemaHLSL/BuiltIns/clamp-errors-16bit.hlsl
M clang/test/SemaHLSL/BuiltIns/clamp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/dot-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/exp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/firstbithigh-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/firstbitlow-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/fmod-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/lerp-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/mad-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/reversebits-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/round-errors.hlsl
M clang/test/SemaOpenCL/invalid-kernel-attrs.cl
M clang/test/lit.cfg.py
A clang/test/utils/update_cc_test_checks/Inputs/filter_out_after.c
A clang/test/utils/update_cc_test_checks/Inputs/filter_out_after.c.expected
A clang/test/utils/update_cc_test_checks/filter_out_after.test
M clang/tools/CMakeLists.txt
A clang/tools/cir-lsp-server/CMakeLists.txt
A clang/tools/cir-lsp-server/cir-lsp-server.cpp
A clang/tools/cir-translate/CMakeLists.txt
A clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-format/git-clang-format
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M clang/www/make_cxx_dr_status
A cmake/Modules/FindLibcCommonUtils.cmake
M cmake/Modules/FindPrefixFromConfig.cmake
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
M compiler-rt/lib/ctx_profile/CtxInstrProfiling.h
M compiler-rt/lib/ctx_profile/tests/CtxInstrProfilingTest.cpp
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPort.h
M compiler-rt/lib/profile/InstrProfilingUtil.c
M compiler-rt/lib/profile/InstrProfilingUtil.h
M compiler-rt/test/asan/TestCases/Darwin/suppressions-sandbox.cpp
M compiler-rt/test/asan/lit.cfg.py
M compiler-rt/test/profile/Posix/instrprof-fork.c
M compiler-rt/test/profile/instrprof-darwin-exports.c
A compiler-rt/test/profile/instrprof-no-mmap-during-merging.c
M flang-rt/README.md
M flang-rt/cmake/modules/GetToolchainDirs.cmake
M flang-rt/include/flang-rt/runtime/descriptor.h
M flang-rt/lib/runtime/transformational.cpp
M flang-rt/unittests/Runtime/Transformational.cpp
M flang/docs/ArrayRepacking.md
M flang/include/flang/Lower/ConvertVariable.h
M flang/include/flang/Lower/LoweringOptions.def
M flang/include/flang/Optimizer/Builder/Runtime/Transformational.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Runtime/transformational.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/Runtime/Transformational.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Support/Fortran.cpp
M flang/module/ieee_arithmetic.f90
M flang/test/Fir/CUDA/cuda-shared-offset.mlir
M flang/test/Fir/CUDA/cuda-shared-to-llvm.mlir
A flang/test/Fir/do_concurrent.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M flang/test/HLFIR/order_assignments/forall-pointer-assignment-scheduling.f90
A flang/test/Lower/CUDA/cuda-shared.cuf
M flang/test/Lower/OpenMP/declare-mapper.f90
M flang/test/Lower/OpenMP/distribute.f90
M flang/test/Lower/OpenMP/order-clause.f90
A flang/test/Lower/OpenMP/threadprivate-common-block-pointer.f90
A flang/test/Lower/repack-arrays.f90
M flang/test/Semantics/OpenMP/metadirective-common.f90
A flang/test/Semantics/OpenMP/test_taskloop_lastprivate_semantic_restrictions.f90
A flang/test/Semantics/OpenMP/test_taskloop_reduction_semantic_restrictions.f90
M flang/test/Semantics/cuf09.cuf
M flang/test/Semantics/cuf13.cuf
A flang/test/Transforms/debug-dummy-argument.fir
M flang/test/Transforms/stack-arrays-hlfir.f90
M flang/tools/bbc/bbc.cpp
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_dl_phdr_info.h
M libc/include/CMakeLists.txt
R libc/include/link.h.def
M libc/include/link.yaml
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__dl_iterate_phdr_callback_t.h
A libc/include/llvm-libc-types/struct_dl_phdr_info.h
M libc/include/search.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/add_sub.h
A libc/src/link/CMakeLists.txt
A libc/src/link/dl_iterate_phdr.cpp
A libc/src/link/dl_iterate_phdr.h
M libc/src/sched/linux/sched_getcpucount.cpp
M libc/src/search/CMakeLists.txt
M libc/src/search/lfind.cpp
A libc/src/search/lsearch.cpp
A libc/src/search/lsearch.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
R libc/src/stdio/scanf_core/converter.cpp
M libc/src/stdio/scanf_core/converter.h
M libc/src/stdio/scanf_core/current_pos_converter.h
R libc/src/stdio/scanf_core/float_converter.cpp
M libc/src/stdio/scanf_core/float_converter.h
R libc/src/stdio/scanf_core/int_converter.cpp
M libc/src/stdio/scanf_core/int_converter.h
R libc/src/stdio/scanf_core/ptr_converter.cpp
M libc/src/stdio/scanf_core/ptr_converter.h
M libc/src/stdio/scanf_core/reader.h
R libc/src/stdio/scanf_core/scanf_main.cpp
M libc/src/stdio/scanf_core/scanf_main.h
R libc/src/stdio/scanf_core/string_converter.cpp
M libc/src/stdio/scanf_core/string_converter.h
A libc/src/stdio/scanf_core/string_reader.h
M libc/src/stdio/scanf_core/vfscanf_internal.h
M libc/src/stdio/sscanf.cpp
M libc/src/stdio/vsscanf.cpp
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/ErrnoCheckingTest.h
M libc/test/src/math/AddTest.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/SubTest.h
A libc/test/src/math/add_same_type_test.cpp
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/SubTest.h
A libc/test/src/math/smoke/add_same_type_test.cpp
A libc/test/src/math/smoke/sub_same_type_test.cpp
A libc/test/src/math/sub_same_type_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/lsearch_test.cpp
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/scanf_core/converter_test.cpp
M libc/test/src/stdio/scanf_core/reader_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/unlink_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
A libc/utils/docgen/glob.yaml
A libc/utils/docgen/sys/utsname.yaml
M libc/utils/hdrgen/hdrgen/header.py
M libclc/CMakeLists.txt
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__algorithm/inplace_merge.h
M libcxx/include/__charconv/tables.h
M libcxx/include/__charconv/to_chars_base_10.h
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__charconv/to_chars_result.h
M libcxx/include/__charconv/traits.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/__functional/binary_function.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/unary_function.h
M libcxx/include/__functional/weak_result_type.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__mutex/once_flag.h
M libcxx/include/__numeric/gcd_lcm.h
M libcxx/include/__numeric/saturation_arithmetic.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/algorithm
M libcxx/include/bitset
M libcxx/include/locale
M libcxx/include/module.modulemap
M libcxx/test/benchmarks/GenerateInput.h
R libcxx/test/benchmarks/algorithms/count.bench.cpp
R libcxx/test/benchmarks/algorithms/equal.bench.cpp
R libcxx/test/benchmarks/algorithms/fill.bench.cpp
R libcxx/test/benchmarks/algorithms/find.bench.cpp
R libcxx/test/benchmarks/algorithms/for_each.bench.cpp
R libcxx/test/benchmarks/algorithms/mismatch.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/fill.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/fill_n.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/generate.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/generate_n.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/move.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/move_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/remove.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/remove_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/replace.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/reverse.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/reverse_copy.bench.cpp
M libcxx/test/benchmarks/algorithms/modifying/rotate.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/rotate_copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/sample.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shift_left.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shift_right.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/shuffle.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/swap_ranges.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/transform.binary.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/transform.unary.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/unique.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/unique_copy.bench.cpp
R libcxx/test/benchmarks/algorithms/move.bench.cpp
R libcxx/test/benchmarks/algorithms/move_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/adjacent_find.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/any_all_none_of.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/contains.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/contains_subrange.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/count.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/ends_with.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/equal.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_end.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_first_of.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/find_last.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/fold.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/for_each.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/is_permutation.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/mismatch.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/search.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/starts_with.bench.cpp
R libcxx/test/benchmarks/algorithms/ranges_contains.bench.cpp
R libcxx/test/benchmarks/algorithms/ranges_ends_with.bench.cpp
R libcxx/test/benchmarks/algorithms/reverse.bench.cpp
R libcxx/test/benchmarks/locale/num_put.bench.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.merge/inplace_merge.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.merge/inplace_merge_comp.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp
M libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_pointer.pass.cpp
M libcxx/test/std/numerics/c.math/hermite.pass.cpp
M libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.local/local_info.members.pass.cpp
M libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp
M libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/types.pass.cpp
M libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
A libcxx/test/support/constexpr_random.h
M libcxx/test/support/counting_predicates.h
M libcxx/test/support/operator_hijacker.h
M libcxx/utils/libcxx/test/features.py
M lldb/bindings/headers.swig
M lldb/include/lldb/API/SBProcess.h
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/StopInfo.h
M lldb/include/lldb/Target/Thread.h
M lldb/include/lldb/Target/ThreadList.h
M lldb/include/lldb/Target/ThreadPlan.h
M lldb/include/lldb/Target/ThreadPlanBase.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/gdbclientutils.py
A lldb/packages/Python/lldbsuite/test/lldbgdbproxy.py
A lldb/packages/Python/lldbsuite/test/lldbreverse.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBThread.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp
M lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
M lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
M lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/scripted/ScriptedProcess.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/CompactUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadList.cpp
M lldb/source/Target/ThreadPlanBase.cpp
M lldb/test/API/functionalities/alias/TestBtAliasRepeat.py
M lldb/test/API/functionalities/breakpoint/breakpoint_locations/TestBreakpointLocations.py
M lldb/test/API/functionalities/data-formatter/data-formatter-objc/TestDataFormatterObjCNSContainer.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/unordered/TestDataFormatterGenericUnordered.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/span/TestDataFormatterLibcxxSpan.py
M lldb/test/API/functionalities/data-formatter/root-reference-children/TestRootReferenceChildren.py
A lldb/test/API/functionalities/reverse-execution/Makefile
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueBreakpoints.py
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueNotSupported.py
A lldb/test/API/functionalities/reverse-execution/TestReverseContinueWatchpoints.py
A lldb/test/API/functionalities/reverse-execution/main.c
M lldb/test/API/lang/cpp/signed_types/TestSignedTypes.py
M lldb/test/API/lang/objc/foundation/TestObjCMethods.py
M lldb/test/API/source-manager/TestSourceManager.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/SetVariableRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
R lldb/tools/lldb-dap/Protocol.cpp
R lldb/tools/lldb-dap/Protocol.h
A lldb/tools/lldb-dap/Protocol/ProtocolBase.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolBase.h
A lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
A lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
A lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/Transport.cpp
M lldb/tools/lldb-dap/Transport.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/unittests/API/SBCommandInterpreterTest.cpp
M lldb/unittests/Core/TelemetryTest.cpp
M lldb/unittests/Platform/CMakeLists.txt
A lldb/unittests/Platform/gdb-server/CMakeLists.txt
A lldb/unittests/Platform/gdb-server/PlatformRemoteGDBServerTest.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
M llvm/CMakeLists.txt
M llvm/Maintainers.md
R llvm/cmake/modules/FindLibcCommonUtils.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-strip.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/DenseSet.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/ADT/SetVector.h
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/include/llvm/ADT/SmallSet.h
M llvm/include/llvm/ADT/StringSet.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/FEntryInserter.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/GlobalMerge.h
M llvm/include/llvm/CodeGen/ModuloSchedule.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/BTF/BTFContext.h
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h
M llvm/include/llvm/DebugInfo/PDB/PDBContext.h
M llvm/include/llvm/DebugInfo/PDB/PDBTypes.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/WrapperFunctionUtils.h
M llvm/include/llvm/Frontend/HLSL/HLSLResource.h
M llvm/include/llvm/IR/Attributes.td
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCInstrAnalysis.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/ELFAttrParserExtended.h
M llvm/include/llvm/Support/JSON.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/FEntryInserter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.h
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
M llvm/lib/DebugInfo/BTF/BTFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/lib/DebugInfo/PDB/PDBContext.cpp
M llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/JSON.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
M llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILLegalizePass.cpp
A llvm/lib/Target/DirectX/DXILLegalizePass.h
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TextAPI/InterfaceFile.cpp
M llvm/lib/TextAPI/TextStubV5.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
A llvm/test/Analysis/BasicAA/call.ll
M llvm/test/Analysis/CostModel/AArch64/aggregates.ll
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fp-conversions-odd-vector-types.ll
M llvm/test/Analysis/CostModel/AArch64/fptoi_sat.ll
M llvm/test/Analysis/CostModel/AArch64/load-to-trunc.ll
M llvm/test/Analysis/CostModel/AArch64/logicalop.ll
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-minmax.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll
M llvm/test/Analysis/CostModel/AArch64/store-ptr.ll
M llvm/test/Analysis/CostModel/AArch64/store.ll
M llvm/test/Analysis/CostModel/AArch64/sve-math.ll
M llvm/test/Analysis/CostModel/AArch64/sve-min-max.ll
M llvm/test/Analysis/CostModel/AArch64/vector-reduce.ll
A llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll
A llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll
R llvm/test/Analysis/CostModel/X86/abs-codesize.ll
R llvm/test/Analysis/CostModel/X86/abs-latency.ll
R llvm/test/Analysis/CostModel/X86/abs-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/abs.ll
R llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
R llvm/test/Analysis/CostModel/X86/arith-int-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-int-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-int-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-int.ll
R llvm/test/Analysis/CostModel/X86/arith-sminmax-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-sminmax-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-sminmax-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-sminmax.ll
R llvm/test/Analysis/CostModel/X86/arith-ssat-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-ssat-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-ssat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-ssat.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-uminmax-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-uminmax.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-codesize.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-latency.ll
R llvm/test/Analysis/CostModel/X86/arith-usat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-usat.ll
R llvm/test/Analysis/CostModel/X86/bitreverse-codesize.ll
R llvm/test/Analysis/CostModel/X86/bitreverse-latency.ll
R llvm/test/Analysis/CostModel/X86/bitreverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse.ll
R llvm/test/Analysis/CostModel/X86/bswap-codesize.ll
R llvm/test/Analysis/CostModel/X86/bswap-latency.ll
R llvm/test/Analysis/CostModel/X86/bswap-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bswap.ll
R llvm/test/Analysis/CostModel/X86/ctlz-codesize.ll
R llvm/test/Analysis/CostModel/X86/ctlz-latency.ll
R llvm/test/Analysis/CostModel/X86/ctlz-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/ctlz.ll
R llvm/test/Analysis/CostModel/X86/ctpop-codesize.ll
R llvm/test/Analysis/CostModel/X86/ctpop-latency.ll
R llvm/test/Analysis/CostModel/X86/ctpop-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/ctpop.ll
R llvm/test/Analysis/CostModel/X86/cttz-codesize.ll
R llvm/test/Analysis/CostModel/X86/cttz-latency.ll
R llvm/test/Analysis/CostModel/X86/cttz-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/cttz.ll
R llvm/test/Analysis/CostModel/X86/div-codesize.ll
R llvm/test/Analysis/CostModel/X86/div-latency.ll
R llvm/test/Analysis/CostModel/X86/div-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/div.ll
R llvm/test/Analysis/CostModel/X86/fcmp-codesize.ll
R llvm/test/Analysis/CostModel/X86/fcmp-latency.ll
R llvm/test/Analysis/CostModel/X86/fcmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fcmp.ll
R llvm/test/Analysis/CostModel/X86/fmaxnum-codesize.ll
R llvm/test/Analysis/CostModel/X86/fmaxnum-latency.ll
R llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll
M llvm/test/Analysis/CostModel/X86/fmaxnum.ll
R llvm/test/Analysis/CostModel/X86/fminnum-codesize.ll
R llvm/test/Analysis/CostModel/X86/fminnum-latency.ll
R llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll
M llvm/test/Analysis/CostModel/X86/fminnum.ll
M llvm/test/Analysis/CostModel/X86/fptosi.ll
M llvm/test/Analysis/CostModel/X86/fptoui.ll
R llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
R llvm/test/Analysis/CostModel/X86/fshl-latency.ll
R llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
R llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
R llvm/test/Analysis/CostModel/X86/fshr-latency.ll
R llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
R llvm/test/Analysis/CostModel/X86/icmp-codesize.ll
R llvm/test/Analysis/CostModel/X86/icmp-latency.ll
R llvm/test/Analysis/CostModel/X86/icmp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/icmp.ll
M llvm/test/Analysis/CostModel/X86/icmp0.ll
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
R llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
R llvm/test/Analysis/CostModel/X86/mul-codesize.ll
R llvm/test/Analysis/CostModel/X86/mul-latency.ll
R llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul.ll
M llvm/test/Analysis/CostModel/X86/mul32.ll
M llvm/test/Analysis/CostModel/X86/mul64.ll
M llvm/test/Analysis/CostModel/X86/reduce-add.ll
M llvm/test/Analysis/CostModel/X86/reduce-and.ll
M llvm/test/Analysis/CostModel/X86/reduce-fadd.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmax.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmin.ll
M llvm/test/Analysis/CostModel/X86/reduce-fmul.ll
M llvm/test/Analysis/CostModel/X86/reduce-mul.ll
M llvm/test/Analysis/CostModel/X86/reduce-or.ll
M llvm/test/Analysis/CostModel/X86/reduce-smax.ll
M llvm/test/Analysis/CostModel/X86/reduce-smin.ll
M llvm/test/Analysis/CostModel/X86/reduce-umax.ll
M llvm/test/Analysis/CostModel/X86/reduce-umin.ll
M llvm/test/Analysis/CostModel/X86/reduce-xor.ll
M llvm/test/Analysis/CostModel/X86/reduction.ll
R llvm/test/Analysis/CostModel/X86/rem-codesize.ll
R llvm/test/Analysis/CostModel/X86/rem-latency.ll
R llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
R llvm/test/Analysis/CostModel/X86/select-codesize.ll
R llvm/test/Analysis/CostModel/X86/select-latency.ll
R llvm/test/Analysis/CostModel/X86/select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/select.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-broadcast-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-extract_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-load-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-load.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i1-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i1.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i32-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i32.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i64-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i64.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-replication-i8-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-replication-i8.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-reverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-reverse.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-select-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-select.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-single-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-single-src.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-splice-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-splice.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
R llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
M llvm/test/Analysis/CostModel/X86/sitofp.ll
R llvm/test/Analysis/CostModel/X86/trunc-codesize.ll
R llvm/test/Analysis/CostModel/X86/trunc-latency.ll
R llvm/test/Analysis/CostModel/X86/trunc-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/trunc.ll
M llvm/test/Analysis/CostModel/X86/uitofp.ll
R llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
R llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
A llvm/test/CodeGen/AArch64/aarch64-sve-ldst-one.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
A llvm/test/CodeGen/AArch64/complex-deinterleaving-unrolled-cdot.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/cttz.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
A llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilege.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehi.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilehs.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilele.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilelo.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilels.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilelt.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilerw.mir
M llvm/test/CodeGen/AArch64/sve-ptest-removal-whilewr.mir
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
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M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
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M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
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M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
A llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
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M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
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M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
A llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
A llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
A llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
A llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
A llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
A llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/int64ops.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/propagate-function-flags-test.ll
A llvm/test/CodeGen/DirectX/legalize-i64-extract-insert-elements.ll
A llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalarize-two-calls.ll
A llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-issue128714.mir
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
A llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
M llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll
A llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
M llvm/test/CodeGen/PowerPC/f128-conv.ll
M llvm/test/CodeGen/PowerPC/fp128-libcalls.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
M llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/mma-outer-product.ll
M llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
A llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/double-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
R llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
M llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
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M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
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M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
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M llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/stores-of-loads-merging.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-composite.ll
A llvm/test/CodeGen/SPIRV/pointers/load-struct.ll
A llvm/test/CodeGen/X86/combine-fma-negate.ll
A llvm/test/CodeGen/X86/fentry.mir
M llvm/test/CodeGen/X86/gfni-lzcnt.ll
M llvm/test/CodeGen/X86/nocf_check.ll
A llvm/test/CodeGen/X86/pr131389.ll
M llvm/test/CodeGen/X86/vector-lzcnt-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-trunc-nowrap.ll
A llvm/test/MC/AArch64/build-attributes-asm-arch-specific-empty.s
A llvm/test/MC/AArch64/build-attributes-asm-arch-specific.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx10.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rvv/aliases.s
A llvm/test/MC/RISCV/rvzfbfmin-aliases-valid.s
M llvm/test/MC/RISCV/rvzfh-aliases-valid.s
M llvm/test/MC/RISCV/rvzfh-pseudos.s
A llvm/test/MC/RISCV/rvzfhmin-aliases-valid.s
A llvm/test/MC/RISCV/xqcibi-invalid.s
A llvm/test/MC/RISCV/xqcibi-valid.s
A llvm/test/MC/RISCV/xqcisim-invalid.s
A llvm/test/MC/RISCV/xqcisim-valid.s
M llvm/test/MC/X86/abs8.s
A llvm/test/TableGen/isa-non-primary.td
M llvm/test/TableGen/x86-fold-tables.inc
A llvm/test/Transforms/GlobalMerge/constants.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/select-icmp-and.ll
M llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
A llvm/test/Transforms/LoopUnroll/pr131465.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
A llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
A llvm/test/Transforms/LoopVectorize/X86/pr131359-dead-for-splice.ll
M llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
A llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/PGOProfile/ctx-instrumentation.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-pattern.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/extract-ordering.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/phi-result-use-order.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
A llvm/test/Transforms/SLPVectorizer/X86/empty-vectorizable-tree.ll
A llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
A llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
M llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
M llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
A llvm/test/Verifier/memset-pattern-unsized.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after.ll.expected2
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after2.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after2.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after3.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/filter-out-after3.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/filter_out_after.test
M llvm/test/tools/llc/new-pm/option-conflict.ll
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
A llvm/test/tools/llvm-readtapi/compare-rpath-order.test
A llvm/test/tools/llvm-reduce/reduce-linkage-intrinsic-global-variables.ll
M llvm/tools/llc/NewPMDriver.cpp
M llvm/tools/llc/llc.cpp
M llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
M llvm/tools/llvm-objdump/ELFDump.cpp
M llvm/tools/llvm-objdump/MachODump.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readtapi/DiffEngine.cpp
M llvm/tools/llvm-reduce/deltas/ReduceGlobalValues.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
M llvm/unittests/ADT/DenseSetTest.cpp
M llvm/unittests/ADT/STLExtrasTest.cpp
M llvm/unittests/ADT/SetVectorTest.cpp
M llvm/unittests/ADT/SmallPtrSetTest.cpp
M llvm/unittests/ADT/SmallSetTest.cpp
M llvm/unittests/ADT/StringSetTest.cpp
M llvm/unittests/DebugInfo/BTF/BTFParserTest.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/PDBVariantTest.cpp
M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Utils/SSAUpdaterBulkTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Core/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Tooling/DependencyScanning/BUILD.gn
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
M llvm/utils/lit/lit/llvm/config.py
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/CommonFolders.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Ptr/IR/CMakeLists.txt
A mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h
A mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
A mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrTypes.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Analysis/SliceAnalysis.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitCPass.cpp
M mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/SubsetInsertionOpInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/Dialect/Quant/Transforms/StripFuncQuantTypes.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseIterationToScf.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Utils/IndexingUtils.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Tools/PDLL/CodeGen/MLIRGen.cpp
M mlir/lib/Transforms/GenerateRuntimeVerification.cpp
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
A mlir/test/Conversion/SCFToEmitC/scf-to-emitc-failed.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/transform-op-pack.mlir
M mlir/test/Dialect/Linalg/vectorization-unsupported.mlir
M mlir/test/Dialect/Ptr/layout.mlir
M mlir/test/Dialect/Ptr/types.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Integration/Dialect/MemRef/cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/MemRef/dim-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/load-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/reinterpret-cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/subview-runtime-verification.mlir
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
A mlir/test/Target/LLVMIR/openmp-distribute-private.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
A mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Transforms/loop-invariant-subset-hoisting.mlir
M mlir/test/lib/Analysis/TestCFGLoopInfo.cpp
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
M mlir/test/lib/Dialect/Test/TestAttributes.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/State.cpp
M offload/include/Shared/Utils.h
M openmp/runtime/src/kmp_sched.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/ce81ce10ff9a...22583d0cf6b8
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