[all-commits] [llvm/llvm-project] 480202: [RISCV] Add Zilsd and Zclsd Extensions (#131094)

[dong-miao via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 480202f0d16f7dbc5c650aea6e8dfd9eca5b999d
      https://github.com/llvm/llvm-project/commit/480202f0d16f7dbc5c650aea6e8dfd9eca5b999d
  Author: dong-miao <601183878 at qq.com>
  Date:   2025-03-19 (Wed, 19 Mar 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/rv32zclsd-invalid.s
    A llvm/test/MC/RISCV/rv32zclsd-valid.s
    A llvm/test/MC/RISCV/rv32zilsd-invalid.s
    A llvm/test/MC/RISCV/rv32zilsd-valid.s
    M llvm/test/MC/RISCV/rv64c-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Zilsd and Zclsd Extensions (#131094)

This commit adds the Load/Store pair instructions (Zilsd) and Compressed
Load/Store pair instructions (Zclsd).

[Specification
link](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc).



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