[all-commits] [llvm/llvm-project] 3c8c29: [NVPTX] Improve 64bit FSH/ROT lowering when shift ...

[Alex MacLean via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c8c2914e067e132af951f70d2b3577fe049e19a
      https://github.com/llvm/llvm-project/commit/3c8c2914e067e132af951f70d2b3577fe049e19a
  Author: Alex MacLean <amaclean at nvidia.com>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/test/CodeGen/NVPTX/rotate.ll
    M llvm/test/CodeGen/NVPTX/rotate_64.ll

  Log Message:
  -----------
  [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (#131371)

When the sift amount of a 64-bit funnel-shift or rotate is constant, it
may be decomposed into two 32-bit funnel-sifts. This ensures that we
recover any possible performance losses associated with the correctness
fix in a131fbf1.

In order to efficiently represent the expansion with Selection DAG
nodes, NVPTXISD::BUILD_VECTOR and NVPTXISD::UNPACK_VECTOR are added
which allow the vector output/input to be represented as a scalar. In
the future, if we add support for the v2i32 type to the NVPTX backend
these nodes may be removed.



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