[all-commits] [llvm/llvm-project] a274ea: [RISCV] Call SimplifyDemandedBits on the scalar in...

[ming via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a274ea1e3a3e1a824e876732074e4638e197b076
      https://github.com/llvm/llvm-project/commit/a274ea1e3a3e1a824e876732074e4638e197b076
  Author: ming <99472920+yanming123456 at users.noreply.github.com>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

  Log Message:
  -----------
  [RISCV] Call SimplifyDemandedBits on the scalar input of vmv_s_x_vl (#131711)

The vmv.s.x instruction copies the scalar integer register to element 0
of the destination vector register. If SEW < XLEN, the least-significant
bits are copied and the upper XLEN-SEW bits are ignored.

Co-authored-by: yanming <ming.yan at terapines.com>



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