[all-commits] [llvm/llvm-project] 467e5a: [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) ...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 467e5a1d41d63fd1c80fee14a8d99d32515c26d6
      https://github.com/llvm/llvm-project/commit/467e5a1d41d63fd1c80fee14a8d99d32515c26d6
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/xqcisim-invalid.s
    A llvm/test/MC/RISCV/xqcisim-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)

This extension adds 10 instructions that provide hints to the interface
simulation environment.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/

This patch adds assembler only support.



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