[all-commits] [llvm/llvm-project] 2175c6: [RISCV] Set AllocationPriority in line with LMUL (...

Philip Reames via All-commits all-commits at lists.llvm.org
Tue Mar 18 08:26:10 PDT 2025 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2175c6cb38e7bb7701219a5081f22e7877ab0380
      https://github.com/llvm/llvm-project/commit/2175c6cb38e7bb7701219a5081f22e7877ab0380
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/expandload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
    M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
    M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext.ll
    M llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Set AllocationPriority in line with LMUL (#131176)

This mechanism causes the greedy register allocator to prefer allocating
register classes with higher priority first. This helps to ensure that
high LMUL registers obtain a register without having to go through the
eviction mechanism. In practice, it seems to cause a bunch of code
churn, and some minor improvement around widening and narrowing
operations.

In a few of the widening tests, we have what look like code size
regressions because we end up with two smaller register class copies
instead of one larger one after the instruction. However, in any larger
code sequence, these are likely to be folded into the producing
instructions. (But so were the wider copies after the operation.)

Two observations:
1) We're not setting the greedy-regclass-priority-trumps-globalness flag
   on the register class, so this doesn't help long mask ranges.  I
   thought about doing that, but the benefit is non-obvious, so I
   decided it was worth a separate change at minimum.
2) We could arguably set the priority higher for the register classes
   that exclude v0.  I tried that, and it caused a whole bunch of
   further churn.  I may return to it in a separate patch.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list