[all-commits] [llvm/llvm-project] bdb632: [AMDGPU][CodeGen] Using MBB's liveIn check in tand...

[Vikash Gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bdb63208b4130aa3811c6f8b6b8b82c5b069eca9
      https://github.com/llvm/llvm-project/commit/bdb63208b4130aa3811c6f8b6b8b82c5b069eca9
  Author: Vikash Gupta <Vikash.Gupta at amd.com>
  Date:   2025-03-18 (Tue, 18 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir

  Log Message:
  -----------
  [AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)

This patch replaces use of MachineRegisterInfo's liveIn check with the
machine basicBlock's liveIn. As the MRI's liveIn is inconsistent with
the entry MBB liveIns, when it comes to the machine verifier checks.

PS: Its an alternative solution with respect to #126926.



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