[all-commits] [llvm/llvm-project] 5bf3f0: [RISCV] Update some of the RVV memory ops in SiFiv...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5bf3f08cc9676ad2ec9b56013f5b3627ce43da7d
      https://github.com/llvm/llvm-project/commit/5bf3f08cc9676ad2ec9b56013f5b3627ce43da7d
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-03-17 (Mon, 17 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s

  Log Message:
  -----------
  [RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)

This patch updates the latencies as well as occupancies of unit stride,
strided, and indexed load/store instructions in SiFive P400 & P600
scheduling models.



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