[all-commits] [llvm/llvm-project] 0c34d7: [mlir][tosa] Require operand/result tensors of at ...

[Luke Hutton via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0c34d7a9e7a4b5d249dda46ff8ab754cf3f934c7
      https://github.com/llvm/llvm-project/commit/0c34d7a9e7a4b5d249dda46ff8ab754cf3f934c7
  Author: Luke Hutton <luke.hutton at arm.com>
  Date:   2025-03-17 (Mon, 17 Mar 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
    M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
    M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
    M mlir/test/Dialect/Tosa/canonicalize.mlir
    M mlir/test/Dialect/Tosa/invalid.mlir

  Log Message:
  -----------
  [mlir][tosa] Require operand/result tensors of at least rank 1 for some operations (#131335)

This commit updates the following operations (operands/results) to be of
at least rank 1 such that it aligns with the expectations of the
specification:
- ARGMAX (input)
- REDUCE_ALL (input/output)
- REDUCE_ANY (input/output)
- REDUCE_MAX (input/output)
- REDUCE_MIN (input/output)
- REDUCE_PRODUCT (input/output)
- REDUCE_SUM (input/output)
- CONCAT (each input in input1/output)
- PAD (input1/output)
- REVERSE (input1/output)
- SLICE (input1/output)
- TILE (input1/output)
- TRANSPOSE (input1/output)

In addition to this change, PAD has been updated to allow unranked
tensors for input1/output, inline with other operations.



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