[all-commits] [llvm/llvm-project] 17e138: [AMDGPU][SIFoldOperands] Fold some redundant bitmasks

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/sifold-bitmasks
  Home:   https://github.com/llvm/llvm-project
  Commit: 17e13825f173be8fd67494f13f002f35d93e357f
      https://github.com/llvm/llvm-project/commit/17e13825f173be8fd67494f13f002f35d93e357f
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-03-17 (Mon, 17 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
    M llvm/test/CodeGen/AMDGPU/si-fold-bitmasks.mir

  Log Message:
  -----------
  [AMDGPU][SIFoldOperands] Fold some redundant bitmasks

Instructions like shifts only read some of the bits of the shift amount operand, between 4 and 6 bits.
If the source operand is being masked, we can just ignore the mask.

Effects are minimal right now but this will kick in more once we disable uniform i16 operation widening in CGP.
With that disabled, we get more i16 shift amounts
that are zext'd and without this we'd end up with
more `s_and_b32 s1, s1, 0xFFFF` in the output.

Ideally ISel should handle this but it's proving difficult to get the patterns right, and after a few hours of trying I just decided to go with this as it's simple enough and it "just works" for this purpose.


  Commit: c18d66f0471be32f8696bea35d749c780f0d785e
      https://github.com/llvm/llvm-project/commit/c18d66f0471be32f8696bea35d749c780f0d785e
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-03-17 (Mon, 17 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

  Log Message:
  -----------
  clang-format


Compare: https://github.com/llvm/llvm-project/compare/65de524db293...c18d66f0471b

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