[all-commits] [llvm/llvm-project] 7af3d3: [SystemZ] Optimize vector comparison reductions

Sat Mar 15 10:29:38 PDT 2025

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7af3d3929e8523cad144ea94551328ce103f9d68
      https://github.com/llvm/llvm-project/commit/7af3d3929e8523cad144ea94551328ce103f9d68
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    A llvm/test/CodeGen/SystemZ/vec-reduce-cmp.ll

  Log Message:
  -----------
  [SystemZ] Optimize vector comparison reductions

Generate efficient code using the condition code set by the
VECTOR (FP) COMPARE family of instructions to implement
vector comparison reductions, e.g. as resulting from
__builtin_reduce_and/or of some vector comparsion.

Fixes: https://github.com/llvm/llvm-project/issues/129434

  Commit: cdc786498650c028c9c8ce23dfbff81bf2780d14
      https://github.com/llvm/llvm-project/commit/cdc786498650c028c9c8ce23dfbff81bf2780d14
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperators.td
    M llvm/test/CodeGen/SystemZ/int-mul-16.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-07.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-08.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-09.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-10.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-11.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-12.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-13.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-14.ll

  Log Message:
  -----------
  [SystemZ] Optimize widening and high-word vector multiplication

Detect (non-intrinsic) IR patterns corresponding to the semantics
of the various widening and high-word multiplication instructions.

Specifically, this is done by:
- Recognizing even/odd widening multiplication patterns in DAGCombine
- Recognizing widening multiply-and-add on top during ISel
- Implementing the standard MULHS/MUHLU IR opcodes
- Detecting high-word multiply-and-add (which common code does not)

Depending on architecture level, this can support all integer
vector types as well as the scalar i128 type.

Fixes: https://github.com/llvm/llvm-project/issues/129705

  Commit: 4a4987be360ac7e4caad65bed54de4ed1d9342ed
      https://github.com/llvm/llvm-project/commit/4a4987be360ac7e4caad65bed54de4ed1d9342ed
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
    M llvm/test/CodeGen/SystemZ/vec-cmpsel.ll
    M llvm/test/CodeGen/SystemZ/vec-move-23.ll
    M llvm/test/CodeGen/SystemZ/vec-shift-07.ll
    A llvm/test/CodeGen/SystemZ/vec-unpack-01.ll
    A llvm/test/CodeGen/SystemZ/vec-unpack-02.ll
    A llvm/test/CodeGen/SystemZ/vec-unpack-03.ll
    A llvm/test/CodeGen/SystemZ/vec-unpack-04.ll

  Log Message:
  -----------
  [SystemZ] Optimize vector zero/sign extensions

Generate more efficient code for zero or sign extensions where
the source is a subvector generated via SHUFFLE_VECTOR.

Specifically, recognize patterns corresponding to (series of)
VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO
DOUBLEWORD instruction.

As a special case, also handle zero or sign extensions of a
vector element to i128.

Fixes: https://github.com/llvm/llvm-project/issues/129576
Fixes: https://github.com/llvm/llvm-project/issues/129899

  Commit: 4155cc0fb3198b1aa4b8e6601980f418c0428cf7
      https://github.com/llvm/llvm-project/commit/4155cc0fb3198b1aa4b8e6601980f418c0428cf7
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperators.td
    A llvm/test/CodeGen/SystemZ/int-cmp-65.ll
    A llvm/test/CodeGen/SystemZ/vec-cmp-10.ll

  Log Message:
  -----------
  [SystemZ] Recognize carry/borrow computation

Generate code using the VECTOR ADD COMPUTE CARRY and
VECTOR SUBTRACT COMPUTE BORROW INDICATION instructions
to implement open-coded IR with those semantics.

Handles integer vector types as well as i128.

Fixes: https://github.com/llvm/llvm-project/issues/129608

  Commit: f4ea1055ad574e0e17fe19662a8c8bcf17e64bfe
      https://github.com/llvm/llvm-project/commit/f4ea1055ad574e0e17fe19662a8c8bcf17e64bfe
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperators.td
    M llvm/test/CodeGen/SystemZ/rot-03.ll
    M llvm/test/CodeGen/SystemZ/shift-16.ll
    A llvm/test/CodeGen/SystemZ/shift-17.ll
    M llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll

  Log Message:
  -----------
  [SystemZ] Implement i128 funnel shifts

These can be handled via the VECTOR SHIFT LEFT/RIGHT DOUBLE
family of instructions, depending on architecture level.

Fixes: https://github.com/llvm/llvm-project/issues/129955

Compare: https://github.com/llvm/llvm-project/compare/86ae25d2be59...f4ea1055ad57

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