[all-commits] [llvm/llvm-project] e6382f: SelectionDAG: neg (and x, 1) --> SIGN_EXTEND_INR...

[Matthias Braun via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6382f2111353f5af66bb660c2e0317c21c398ed
      https://github.com/llvm/llvm-project/commit/e6382f2111353f5af66bb660c2e0317c21c398ed
  Author: Matthias Braun <matze at braunis.de>
  Date:   2025-03-14 (Fri, 14 Mar 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
    M llvm/test/CodeGen/AArch64/pr61111.ll

  Log Message:
  -----------
  SelectionDAG: neg (and x, 1)  -->  SIGN_EXTEND_INREG x, i1 (#131239)

The pattern
```LLVM
%shl = shl i32 %x, 31
%ashr = ashr i32 %shl, 31
```
would be combined to `SIGN_EXTEND_INREG %x, ValueType:ch:i1` by
SelectionDAG.
However InstCombine normalizes this pattern to:
```LLVM
%and = and i32 %x, 1
%neg = sub i32 0, %and
```
This adds matching code to DAGCombiner to catch this variant as well.



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