[all-commits] [llvm/llvm-project] b9bf3f: [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in...

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/combine-sext-trunc-sextinreg
  Home:   https://github.com/llvm/llvm-project
  Commit: b9bf3f2f53fcf7cbd133e57d4c7f64a8f06763b2
      https://github.com/llvm/llvm-project/commit/b9bf3f2f53fcf7cbd133e57d4c7f64a8f06763b2
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2025-03-14 (Fri, 14 Mar 2025)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))

This is a bit of an akward pattern that can come up as a result
of legalization and then widening of i16 operations to i32 in RegBankSelect
on AMDGPU.

This quick combine avoids redundant patterns like
```
s_sext_i32_i8 s0, s0
s_sext_i32_i16 s0, s0
s_ashr_i32 s0, s0, s1
```

With this the second sext is removed as it's redundant.



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