[all-commits] [llvm/llvm-project] a6463f: [RISCV] Shrink the size of the VLMul field in Regi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6463f41135d7d96e92cefeeffa84d0955f934f9
      https://github.com/llvm/llvm-project/commit/a6463f41135d7d96e92cefeeffa84d0955f934f9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-13 (Thu, 13 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Shrink the size of the VLMul field in RegisterClass target flags. Use uint8_t for TSFlags. NFC (#131227)

There are only 4 possible LMULs corresponding to log2 of 1, 2, 4, and 8.
Those fit in 2 bits.

Use uint8_t for the flag bits to match the size in TargetRegisterClass.



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