[all-commits] [llvm/llvm-project] dff22a: [X86] combineConcatVectorOps - convert X86ISD::BLE...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dff22a0c1173f9d1ec0830b1c039749b6c2241d6
      https://github.com/llvm/llvm-project/commit/dff22a0c1173f9d1ec0830b1c039749b6c2241d6
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-03-13 (Thu, 13 Mar 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/masked_store.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll

  Log Message:
  -----------
  [X86] combineConcatVectorOps - convert X86ISD::BLENDI concatenation to use combineConcatVectorOps recursion (#131121)

Only concatenate X86ISD::BLENDI nodes if at least one operand is beneficial to concatenate

Add AVX1/AVX2 handling to 256-bit BLENDI nodes (accounting for AVX2 v16i16 repeated mask requirements).

Extend existing AVX512BW (which still always concats until I get get rid of the remaining regressions) to handle AVX512F for 32/64-bit scalar types.



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