[all-commits] [llvm/llvm-project] bd748b: [RISCV] Add implicit operand {VL, VTYPE} in RISCVI...

[Hank Chang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd748b33958f8889d280afd4396b189edd0745bf
      https://github.com/llvm/llvm-project/commit/bd748b33958f8889d280afd4396b189edd0745bf
  Author: Hank Chang <hank.chang at sifive.com>
  Date:   2025-03-13 (Thu, 13 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    A llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll

  Log Message:
  -----------
  [RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (#130733)

…sing inline assembly.
Fixing [#128636](https://github.com/llvm/llvm-project/pull/128636).

This patch has RISCVInsertVSETVLI to add implicit use operand to inline
assembly, this approach is suggested by @preames and the implementation
I referenced is from @topperc . The purpose of adding vl, vtype implicit
operand is to prevent Post-RA scheduler moving vsetvl across inline
assembly.



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