[all-commits] [llvm/llvm-project] 9a5bfd: AMDGPU/GlobalISel: Temporal divergence lowering (n...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/temporal-divergence
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a5bfd368f40d1c313dc1783df4f43f12b88258b
      https://github.com/llvm/llvm-project/commit/9a5bfd368f40d1c313dc1783df4f43f12b88258b
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-03-12 (Wed, 12 Mar 2025)

  Changed paths:
    M llvm/include/llvm/ADT/GenericUniformityImpl.h
    M llvm/include/llvm/ADT/GenericUniformityInfo.h
    M llvm/lib/Analysis/UniformityAnalysis.cpp
    M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Temporal divergence lowering (non i1)

Record all uses outside cycle with divergent exit during
propagateTemporalDivergence in Uniformity analysis.
With this list of candidates for temporal divergence lowering,
excluding known lane masks from control flow intrinsics,
find sources from inside the cycle that are not i1 and uniform.
Temporal divergence lowering (non i1):
create copy(v_mov) to vgpr, with implicit exec (to stop other
passes from moving this copy outside of the cycle) and use this
vgpr outside of the cycle instead of original uniform source.



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